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This issue is a method of tracking/deconflicting efforts to change the Python API. If anyone has any PRs to change the Python API please let me know and we can record them here! We can also use this i…
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Dear Bambu team,
When using RTL designs generated by Bambu, I constantly get very tight timing after Vivado implementaion(post route timing report), much worse than what Bambu estimated during its ba…
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`oddr` in `Clash.Xilinx.DDR` shares the Haskell simulation model with `ddrOut` in `Clash.Explicit.DDR`. However, they react differently to the `Enable` signal, making the model wrong for Xilinx's `odd…
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With wrappers for builtin floating-point modules (On Intel & Xilinx FPGAs), we have a far more competent language to be used at PC2.
Full parametrizability will likely be blocked by #25, but basic…
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I used the automated make script to generate a Vivado project for FPGA implementation of Vortex. It creates the project however gives error during synthesis:
> [Synth 8-2671] single value range is …
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I am trying to enable secure boot on ARM Zynq board. By studying the boot sequence of the board we found out that it is possible to authenticate with PQC only the partitions starting from the FSBL (si…
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Currently, if you try to use a flip flop with a shaped input, the conversion fails when using `XilinxPlatform`.
Other places in the code might be affected to, I haven't checked that.
To reproduce:…
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There is a Platform config Makefile for Xilinx xrt named platforms.mk, but not for Altera opae. When I try to run opae synthesis in DevCloud, it gives missing DPLATFORM_MEMORY_BANKS, DPLATFORM_MEMORY_…
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Not realy sure if this is a wrong thing about the package, my specific installation or if it has somethign to do with a redeclaration issue (i have another version of xilinx installed), but when tryin…
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Hi, Eugene
Thank you for the open-source project. Could anyone provide insight into the possible causes of this issue or suggest a solution?
I have encountered an issue while attempting to boot a …