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Hi Taichi,
Thanks for taking care of this project! I am trying to compile it with Vivado, but I have some problems with Xelab, so I need some help.
More specifically, I tried these versions and …
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When I try to open the post place & route implementation in fpga_editor from the tools menu, I get this error:
`/opt/Xilinx/14.7/ISE_DS/ISE/bin/lin64/_fpga_editor: error while loading shared librar…
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### Background Work
- [X] Yes, I searched the [mailing list](https://groups.google.com/forum/#!forum/firesim)
- [X] Yes, I searched [prior issues](https://github.com/firesim/firesim/issues)
- [X] Yes…
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I've been using the workflow described in this link https://vhdlwhiz.com/formal-verification-in-vhdl-using-psl/#yosys-et-al
It has afforded me great success, and i've taken my first steps with formal…
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Hi it seems the changes needed for 2021-2023 is minor.
```
diff --git a/examples/alpha250/adc-dac-dma/block_design.tcl b/examples/alpha250/adc-dac-dma/block_design.tcl
index e28f2090..edb64099 10…
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Install fails due to https://github.com/Xilinx/PYNQ-Metadata/issues/20 (versions >0.1.2)
Temporary workaround is to follow https://github.com/Xilinx/PYNQ-Metadata/issues/20#issue-2328202954
and then…
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I am tring to integrate DPU4.1 to ZYNQ-Z2 board. So I choose Vivado 2022.2 and PetaLinux 2022.2 to generate linux image for SD card.
but when I following[ THIS TUTORIAL](https://github.com/Xilinx/Vit…
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I got new TE0712 modules. On a working setup, I replaced an old programmed modules with the new module. I could load the bitfile to FPGA, and the board worked as expected until reboot/repower. Then …
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In aie2xclbin (in mlir-aie) we're looking for a file libc.a: see here https://github.com/Xilinx/mlir-aie/blob/3ac9566f1da7c4ee6e81c263bc15d92aba7bcae7/tools/aie2xclbin/XCLBinGen.cpp#L345
I can in o…
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The error observed:
```
LLVM ERROR: unable to legalize instruction: %512:_() = G_MUL %378:_, %390:_ (in function: core_0_2)
```
Is this instruction multiplying 2 vectors containing 2 32-bit si…