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**Describe the bug**
I want to run the anatomical pipeline in order to continue with the fc pipeline. So far the anatomical pipeline has a few errors ( and cannots). The errors seem occur quite late…
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Hi all,
I have a question about the VLSI flow in Chipyard.
I find that it always fails when I use genus to synthesize the ChipTop module, the top module of a SoC, e.g., the BOOM …
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**What will you do?**
High-level synthesis enables hardware designers to describe the functionality of their accelerators in software languages such as C/C++. While functional simulation can be per…
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Issues
- [x] Depends on R >= 3.5 (Which is okay)
- [x] Data size / Non-ascii characters in the data
- [x] S3 generic
- [x] Triple-colon operator
- [x] base functions
- [x] Missing documentati…
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Hi!
The following question is not about a bug in the code, it is more of an IO overhead question regarding my software-hardware co-design experiments based on Murax SoC. _I am not sure if it is sui…
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Tracking various relevant papers and articles.
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filter broken
**pandocc is installed**
```
~$ pandoc --version
pandoc 2.9.1.1
Compiled with pandoc-types 1.20, texmath 0.12.0.2, skylighting 0.8.4
Default user data directory: /home/kjambunath…
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Hello,
I saw on the website cache isn't implemented yet for Ariane. Is that still the case? Is there any branches that I could test out that uses cache?
Thank you!
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Hi there,
I do see the architectures and a set of constraints of eyeriss, simba and chen-asplos2014, but how could I get the the default dataflows without a mapper? Basically, in addition to datafl…
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Can the bellows library be made to support newer EZSP serial protocol such as EZSP v6, v7, and v8 when used with ZNet 6.x on Silicon Labs EFR32 (Mighty Gecko family) based Zigbee radio adapters?
Se…
Hedda updated
3 years ago