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Synthesizing a counter with asynchronously reset-able count results in:
"../RTL/resetctrl.m.vhdl:37:9:error: synchronous code does not expect else part".
Reproducible with the following archive:
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trcwm updated
3 years ago
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Current component definition:
https://github.com/ghdl/ghdl-yosys-plugin/blob/master/library/ecp5u/components.vhdl#L1489
When compiled I get errors like this:
```
ERROR: Module `MULT18X18D' refer…
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Dear ghdl-yosys-plugin project, first of all thank you for your great work so far. I have a minimal example I can reproduce the 'ERROR: wire not found for $posedge' :
```library IEEE;
use IEEE.std_…
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It doesn't look like ghdl-yosys-plugin is compatible with newest yosys.
Here is the result of me running `make`.
[no_more_build.txt](https://github.com/ghdl/ghdl-yosys-plugin/files/4616591/no_mo…
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It seems that you are using, or suggesting to use, docker images that are maintained/released from ghdl/docker, in order to avoid building ghdl and ghdl-yosys-plugin. Precisely image `ghdl/synth:beta`…
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Description: When an FSM in a specific implementation using a state with no initialization value used, it is recognized by yosys to be recoded as 'one-hot'. Synthesis then produces a non-functional re…
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**Description**
libghdlsynth.a is not possible target any more. It is needed by static version of ghdl-yosys-plugin available here https://github.com/ghdl/ghdl-yosys-plugin/blob/master/yosys.diff
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Hi @mithro, I read your document, but I need more info about that point :P I will check how to use Conda, and I need an environment which supports:
* Yosys, GHDL and the ghdl-yosys-plugin, iverilog, …
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Scenario: Instancing a RAM element:
```
init_ram_l:
DPRAM16_init_hex_ce
generic map ( ADDR_W => ADDR_W, DATA_W => DATA_W,
INIT_HEX => "test_a.hex" )
port map (..)
```
from a Verilog impl…