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Traceback (most recent call last):
File "./RestructureNetlistSkywater.py", line 1033, in
main()
File "./RestructureNetlistSkywater.py", line 169, in main
m = from_verilog.read_verilog…
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Hi!
My use case is described in #1780, but I will give more details. I'm looking to build a node-based programming environment entirely within the browser, most notably with [WebUSB](https://web.de…
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It would be nice to have the Parser/Validator API return an object with full file parsing/validation errors ( or competed successfully ) rather than halting at the first exception.
I believe you do…
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Hello,
I tried to simulate a simple verilog-a file in Xyce. It works until one of the inputs reaches zero and then fails. The idea is that the output should flip phase of the input when that input …
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It would be useful to see a minimal example script to create a design like the one in the documentation (https://byuccl.github.io/spydrnet/docs/stable/reference/classes/index.html#fig-exampleir) from …
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Dear community,
Hello I'm currently working on building a kernel image following DPU-TRD Vitis flow: https://github.com/Xilinx/Vitis-AI/blob/1.3.1/dsa/DPU-TRD/prj/Vitis/README.md **with zcu106 bo…
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I compiled Xyce in Linux Manjaro without issues. The same setup was used to simulate in Xyce 7.2. When I try to use HB simulation, it dies with the following message:
***** Beginning Transient Calcul…
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I tried to run the JTAG port insertion command but following error caused exiting the process. Is it a bug or something missing at my end?
```Generating LALR tables
WARNING: 183 shift/reduce conflic…
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I am using the `GenCouplingSimulator` API to build a long-running wrapper around Xyce.
However, I found that when there is a parse error in the arguments or the spice netlist, the `initialize` call j…
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I have just come across an issue with Yosys, where it produces assigns like the following:
`assign {a,b} = {c,d};`
OpenSTA cannot parse these.
Now, the simple approach would be to stop Yosys…