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PyHDI
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Pyverilog
Python-based Hardware Design Processing Toolkit for Verilog HDL
Apache License 2.0
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TypeError: generate() got an unexpected keyword argument 'reorder' line 100 in Pyverilog/examples/example_graphgen.py
#131
zhangshuaiAA9
opened
2 months ago
2
fix: parsing of ansi style localparam declarations
#130
mclark-iontra
opened
3 months ago
0
ANSI Style localparam causes parsing error
#129
mclark-iontra
opened
3 months ago
0
Codegen arrays
#128
CapucinedeBoissac
opened
11 months ago
0
Unsized numbers without base solution
#127
YSJL
opened
11 months ago
0
parser error
#126
1353369570
opened
11 months ago
0
Attribute error in parser
#125
KatCe
opened
11 months ago
0
Parse Error: Cannot parse a function
#124
KatCe
opened
11 months ago
1
Preprocessing Issue when included file is in different directory
#123
YSJL
closed
12 months ago
1
AST node
#122
lijiale6224
opened
1 year ago
1
Can not support "generate case" statement
#121
TonyLiaoZP
opened
1 year ago
0
fix: unexpected keyword argument `reorder`
#120
superpung
opened
1 year ago
4
Added support for automatic functions
#119
Lucaz97
opened
1 year ago
0
unsufficient parse for large scale verilog design
#118
ZhaoYunfei123
opened
1 year ago
0
TypeError: generate() got an unexpected keyword argument 'reorder'
#117
Sanjaya97
opened
1 year ago
3
Unsized numbers without base not supported
#116
Louis-DR
opened
1 year ago
2
Specify statements
#115
lilasrahis
opened
1 year ago
0
Parsing Issues
#114
kwmartin
opened
1 year ago
1
ParseError for User Defined Primitives
#113
TheMatt2
opened
1 year ago
1
Parser Error for resettable D Flip-Flop
#112
kwmartin
opened
1 year ago
1
Parse Error for Inverter Gate
#111
kwmartin
opened
1 year ago
0
Parsing Error for integer memories
#110
kwmartin
opened
2 years ago
0
dataflow analysis error
#109
cemery123
opened
2 years ago
1
Extracting design information via API
#108
svenka3
opened
2 years ago
0
Defparam support
#107
trharoldsen
closed
2 years ago
0
How to setup and install pyverilog inside py virtual environment?
#106
usman1515
closed
2 years ago
1
About control flow analysis
#105
earphonebreaker
opened
2 years ago
0
windows error -run example_parser.py
#104
TobyLQ
closed
2 years ago
1
Support SVA assert/assume
#103
zhanghongce
opened
2 years ago
0
A bug when parsing nesting ifStatement
#102
Yang-Qirui
opened
2 years ago
0
[wip] Add support for functions declarations with port list
#101
noloerino
opened
2 years ago
1
Functions with port lists can't be parsed
#100
noloerino
opened
2 years ago
0
Use context manager to avoid ResourceWarning
#99
leonardt
closed
1 year ago
0
[PARTSELECT PLUS MINUS FIX] Fixed the MSB or LSB computation for the …
#98
lreim
opened
2 years ago
2
TypeError: generate() got an unexpected keyword argument 'reorder'
#97
venkateshknpl
opened
3 years ago
2
error
#96
61cc
opened
3 years ago
0
Modify AST generated by PyVerilog
#95
sazadur
opened
3 years ago
0
How to append new assign to a module from verilog code?
#94
zilongwang123
opened
3 years ago
0
how
#93
zilongwang123
opened
3 years ago
0
Error running example_graphgen.py
#92
zhileiren
opened
3 years ago
1
gate level netlist to rtl
#91
very3b
opened
3 years ago
0
isWireArray(termtype) is missing in /utils/signaltype.py
#90
teaalltr
opened
3 years ago
1
OSError: Format: "dot" not recognized. Use one of:
#89
faruqui13
opened
3 years ago
0
Added end_lineno to indicate the last line number in always, module, …
#88
dyadav7
closed
1 year ago
1
SVA assert / assume/ cover property support
#87
dyadav7
opened
3 years ago
1
question regarding implementation
#86
nancychang42
closed
3 years ago
1
Not able to run
#85
KaranThakur1998
opened
3 years ago
0
ast.IntConst creates collisions on dicts
#84
Lucaz97
opened
3 years ago
2
vparser/parser.py mkdir arguement error
#83
GrantBrown1994
closed
3 years ago
1
Delays incorrectly printed on output to verilog
#82
jandreasen3
opened
3 years ago
1
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