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Hi Chris,
I'm trying to remove some parts from a routed DCP. It seems to be working, but I'm not sure if I missed anything, especially what to do with the physical Net.
Specifically, I try to re…
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Pseudo PIPs are necessary to allow site-thru connections, where an explicit cell is missing, but one is required to let a signal be routed to the destination (e.g. IOI_LOGIC, BUFHCE, etc.).
There …
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Replication instructions (using #126):
```
git clone -b duplicate_pips git@github.com:litghost/RapidWright.git
cd RapidWright
make update_jars
RAPIDWRIGHT_PATH=$(pwd) ./scripts/invoke_rapidwright…
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Run `make test-fpga_interchange-ram_basys3-dcp` in nextpnr and open the DCP in Vivado. There are routing issues (nets in yellow rather than green), `report_route_status` reports the following:
```
…
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I'm currently debugging the Cell BEL pin maps for the RAMB18E1 on 7-series. The current mapping appears to be missing some VCC/GND ties on pins in some configurations.
For example, the pin map f…
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Xilinx vendor tool test fails on master (e.g. https://github.com/SymbiFlow/symbiflow-arch-defs/pull/1912), coinciding with this release: https://github.com/Xilinx/RapidWright/releases/tag/v2020.2.0-be…
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While debugging the Murax design with the interchange format, the following DRC errors were generated:
```
ERROR: [DRC PDRC-131] SLICE_PairEqSame_A6A5_ERROR: Incompatible programming for site SLIC…
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Hi all!
Thanks for your great effort to implement RapidWright.
I am facing a problem where I call getCompatiblePlacements() with a cell in type of LUT3:
_Exception in thread "main" java.lang.…
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Hi Chris,
I wonder if RW will provide a timing-driven router? Seems that only a non-timing-driven one is available currently.
Meanwhile, I tried the timing-driven routing routine in the `Pipelin…
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Command executed:
```
scripts/invoke_rapidwright.sh com.xilinx.rapidwright.interchange.DeviceResourcesExample xcvu19pfsvb3824-1
```
Error:
```
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