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chipsalliance
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python-fpga-interchange
Python interface to FPGA interchange format
ISC License
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VPR generates warnings about missing timing in testarch
#166
sh-mcu8apps
opened
7 months ago
0
Add LUT+FF clustering rule
#165
mkurc-ant
closed
1 year ago
0
Add interchange helper script for REPL mode
#164
kboronski-ant
opened
2 years ago
0
yosys_json: fix prim lib import
#163
acomodi
closed
2 years ago
0
AttributeError when converts IF to json
#162
zhilix
opened
2 years ago
0
Pin pycapnp library to a working version
#161
kiryk
closed
2 years ago
0
Hotfix for #159
#160
mkurc-ant
closed
2 years ago
0
Bus net handling in Yosys JSON to netlist conversion
#159
mkurc-ant
closed
2 years ago
0
Automatic top module detection
#158
mkurc-ant
closed
2 years ago
0
Renamed SymbiFlow references to CHIPS Alliance and F4PGA
#157
kiryk
closed
2 years ago
0
A hotfix for constant sources in device resources builder
#156
mkurc-ant
closed
2 years ago
0
Constant handling in device resources builder
#155
mkurc-ant
closed
2 years ago
0
Device resource builder - pseudo-PIPs
#154
mkurc-ant
closed
2 years ago
0
Test arch packages
#153
acomodi
closed
2 years ago
0
Fix RAM256X1D for xcup
#152
kboronski-ant
closed
2 years ago
0
Fix RAM32X1D expansion and add expansion for RAM256X1D
#151
kboronski-ant
closed
2 years ago
0
Macro clusters for xcup LUT-RAMs
#150
kboronski-ant
closed
2 years ago
3
CI: [Rapidwright] Run make compile before make update_jars
#149
kboronski-ant
closed
2 years ago
0
Enable BUFCE route-through for US+ devices and increase max_hops for global buffers
#148
kboronski-ant
closed
2 years ago
2
[WIP] Importing cell timings from prjxray-db
#147
mkurc-ant
opened
2 years ago
0
testarch: fix IOB cell bel mapping
#146
acomodi
closed
2 years ago
0
Allow multiple LUT elements in site type
#145
mkurc-ant
closed
2 years ago
0
Improve IO pads complexity handling
#144
acomodi
closed
2 years ago
0
Added optional suffix for BBA files
#143
mkurc-ant
closed
2 years ago
0
testarch: add multiple bels in the same site
#142
acomodi
closed
2 years ago
0
Add corner offsets to device_resources_builder.py
#141
mtdudek
closed
2 years ago
0
An option to disable FFMUX in the testarch
#140
mkurc-ant
closed
2 years ago
0
testarch: add more complex cell bel mappings
#139
acomodi
closed
2 years ago
0
Fix lutDefinitions in testarch
#138
mtdudek
closed
2 years ago
0
testarch: fix LUT init param
#137
acomodi
closed
2 years ago
0
Testarch generator: add LUT param definition and use single PAD
#136
acomodi
closed
2 years ago
0
Various fixes
#135
mtdudek
closed
2 years ago
0
testarch: add LUT definitions and INIT param
#134
acomodi
closed
2 years ago
0
Add parameters to library cells
#133
mtdudek
closed
2 years ago
0
Fix testarch generator's primLib
#132
mtdudek
closed
2 years ago
0
testarch: add more arguments to make the testarch gen more flexible
#131
acomodi
closed
2 years ago
0
Fix regex strings
#130
mtdudek
closed
2 years ago
0
clusters: macro: disable other cells in same site with macro clusters
#129
acomodi
closed
2 years ago
0
FASM generators: add LUTRAM support for xc7
#128
acomodi
opened
3 years ago
0
fasm: xc7: add w7/8 used mux
#127
acomodi
closed
3 years ago
0
interchange: increase nesting limit
#126
acomodi
closed
3 years ago
0
Turn off pseudoPIPs going through LUT6 bels in Xilinx 7-series
#125
mtdudek
closed
3 years ago
0
Fix backslash escape by converting any series of them into single backslash
#124
mtdudek
closed
3 years ago
0
Convert macros to clusters for better placement
#123
mtdudek
closed
3 years ago
0
fasm: nexus: fix call to fill_pip_features
#122
acomodi
closed
3 years ago
0
params: add other valid boolean strings when converting str to int
#121
acomodi
closed
3 years ago
0
netlist: fix floating point parameter when converting yosys to netlist
#120
acomodi
closed
3 years ago
0
PLL and MMCM FASM generation
#119
mkurc-ant
closed
3 years ago
0
device data: xcup: disable PPIPs through LUTs
#118
acomodi
closed
3 years ago
0
Issues trying to create YAML device file from example
#117
clavin-xlnx
opened
3 years ago
4
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