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I am not sure what I should set XILINX_BOARD to ? I am using a zybo whose part number is xc7z010clg400-1
since I didn't find the XILINX_BOARD value for my board I just kept the default one ( em.avne…
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I am trying to use netv2-fpga as a develpment board. To use the board in Xilinx Vivado, I need to add the board to Vivado's available boards. This is normally done by adding the board files, including…
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Hi Jamie, this is a very interesting project you have here. I’m thinking of porting the rtl to small xilinx spartan-6 based devices (lx9 and/or lx16) . I was wondering how altera/intel specific your c…
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It would be really good to include some information in the README around the resource usage of microwatt.
I would recommend the following stats;
- [ ] LUT + FF usage
- [ ] Highest fmax possible…
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I have synthesized the system for the U55C target and tried to run it.
It is not booting.
An equivalent system build from the internal repositories work, but the public system does not.
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https://coldnew.github.io/7a67f04e/
手邊有一台早期獲得的 Altera DE2-115 開發平台 ，一直放著積灰塵也不是辦法，再加上最近想多玩玩 FGPA，所以就來重新玩一次吧 :) 和 Xilinx Zybo Board 不同，Altera DE2-115 開發平台 是只有 FPGA 的開發板，並未包含 ARM Cortex-A9 來作為輔助用的 …
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I successfully implemented the FPGA design on a Xilinx Spartan 3AN (xc3s700an) but when I run the mining script miner.py I get a rejection rate of 100%. Might this issue be related to the one discusse…
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Hi,
In the quick start guide, it is mentioned that "After working through this document you should have a [cli_test](https://github.com/openhwgroup/core-v-mcu-cli-test) running on the CORE-V-MCU o…
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Current implementation of AGWB has problems with FPGAs hosting e.g. multiple PCIe devices (an example may be huge Xilinx FPGA with two SLRs).
In that case we may have two independent and slightly dif…
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Sorry, if this is an offtopic, i'll move it to maillist if it's so. This is just common suggestions about "full metal runtime.js/nodejs" related to this #42 and this #43 issues.
Besides all feature…
danxn updated
9 years ago