wzab agwb issues - Githubissues

wzab / agwb

Support for automatic address map generation and address decoding logic for Wishbone connected hierachical systems

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issues

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Automated generation of mutiple registers for width > 32

#68 wzab opened 4 months ago
0
Adding a memory map package in the VHDL outputs so that the VHDL modules can use addresses as constants

#67 lepommosaure opened 9 months ago
0
Explicit register addresses as constants in HDL package

#66 lepommosaure opened 9 months ago
4
Updates from cbm

#65 wzab closed 2 years ago
0
Incorrect code generated when the default value is set in the vector of control registers

#64 wzab closed 2 years ago
1
Potential problem with constants within block declarations.

#63 m-kru opened 3 years ago
0
Certain problems with RelaxNG syntax validation

#62 wzab closed 3 years ago
1
Better handling of BlackBoxes - support for HLS?

#61 wzab opened 3 years ago
9
Connecting Wishbone busses - naming conventions

#60 wzab opened 3 years ago
0
Mistake in wb_cdc?

#59 wzab closed 3 years ago
3
Mixed usage of "downto" and "to" in indexing in AGWB VHDL code

#58 wzab closed 3 years ago
1
Selection between "agwb" and "agwb_dca" does not work correctly now.

#57 wzab opened 3 years ago
1
Python backend support vor variants

#56 wzab closed 3 years ago
3
Implementation of the "extended interface" - to make use of the extended features of IPbus, E2bus or CBM DCA - how to implement RMW?

#55 wzab opened 3 years ago
3
Current CDC block is inefficient for connecting clock domains using synchronous clocks with different frequencies

#54 wzab opened 3 years ago
0
Using the registered Wishbone crossbar in more complex designs

#53 wzab closed 3 years ago
2
Enabling stb generates incompatible port name.

#52 m-kru closed 3 years ago
1
Validation of system description XML with RelaxNG sometimes gives incorrect error reports

#51 wzab closed 3 years ago
2
Add RELAX NG schema.

#50 m-kru closed 3 years ago
1
Adding the test registers at known address locations.

#49 wzab closed 3 years ago
2
Detection of incorrect attributes in system description.

#48 wzab closed 3 years ago
1
Better granularity of the version identifiers.

#47 wzab closed 3 years ago
0
Problem with the newest version of GHDL

#46 wzab closed 3 years ago
4
Generation of multiple AGWB tree instances to be used in the same design

#45 wzab opened 3 years ago
1
Add regression testing.

#44 m-kru opened 3 years ago
0
Split code into packages and modules.

#43 m-kru opened 3 years ago
0
Treating subblock elements as a block instantiation.

#42 m-kru opened 3 years ago
0
Mg dev

#41 gumaas closed 3 years ago
0
Port name for aggregated outputs does not follow the naming convention.

#40 m-kru opened 3 years ago
0
Superfluous assignment in to_slv() functions converting from custom types to std_logic_vector.

#39 m-kru closed 3 years ago
0
Add description for math within value attributes in the docs.

#38 m-kru opened 3 years ago
0
Unify `reps` attribute behavior.

#37 m-kru closed 3 years ago
1
Make 'reps' attribute for register always result with vector.

#36 m-kru closed 3 years ago
0
Revise hdl parameter for FuseSoc wrapper

#35 m-kru closed 3 years ago
1
Unnecessary general_cores dependency.

#34 m-kru closed 3 years ago
0
Document base parameter for agwb.Block class

#33 m-kru opened 3 years ago
0
Rename auto generated VHDL functions converting to std_logic_vector.

#32 m-kru closed 3 years ago
0
Remove agwb_ prefix from VHDL files and entities.

#31 m-kru closed 3 years ago
0
C++ backend - how to enable run-time resolution of addresses

#30 wzab opened 3 years ago
0
Allow installing modules from agwb directory.

#29 m-kru closed 4 years ago
0
Put generated .vhd files in the agwb library when used with FuseSoc.

#28 m-kru closed 4 years ago
0
Do not print template dictionary to stdout.

#27 m-kru closed 4 years ago
0
Reduce amount of console output.

#26 m-kru closed 4 years ago
0
Improve format of VHDL constants generation.

#25 m-kru closed 3 years ago
0
In the HTML documentation the length of object (blocks or register) vectors is not shown

#24 wzab opened 4 years ago
0
Scalability of vectors of subblocks

#23 wzab closed 5 years ago
1
Improved handling of blackboxes

#22 wzab opened 5 years ago
0
Add constants with register addresses to _wb_pkg.vhd files.

#21 m-kru closed 5 years ago
0
Add _const_pkg.vhd file to created files list.

#20 m-kru closed 5 years ago
0
Generate non HDL files under files_root directory.

#19 m-kru closed 5 years ago
0