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Using the ghdl-yosys plugin a "GHDL Bug Occured" is reported when using a 'when x to y' statement (inside a case statement).
It can be reconstructed by saving the code below (testcase1.vhd) and run…
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**Description**
Recent changes to case statements introduced in commit c9d2cccb38b985783108f187398a0a0af9f6ab62 (as found by `git bisect`) result in case statements not being handled correctly.
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# Useful preface:
This request appears because I was [comparing Yosys against ISE and Vivado](https://github.com/rodrigomelo9/yosys-versus), using examples provided by Xilinx. I am now testing with…
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With the latest Yosys GIT HEAD, the VHDL plugin fails to build:
```
yosys-plugins/vhdl$ make
clang -Wall -Wextra -ggdb -I/usr/local/share/yosys/include -MD -D_YOSYS_ -fPIC -I/usr/local/include -s…
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First, thanks for doing this all. Second, I have verified that your core really returns 2 for a "1+1" command issued in micropython "natively" on a Power9 Talos II running Fedora 30 for ppc64le as hos…
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**Description**
I want to build this design https://github.com/wtatarski/Artix-7-HDMI-processing using `ghdl` + `ghdl-yosys-plugin` + `yosys` + `Vivado` (I use 2017.2 version). I managed to build des…
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Hello. I am [analyzing with the plugin](https://github.com/rodrigomelo9/yosys-versus) (branch ghdl) examples provided by Xilinx. I found that latches are unsupported. Here only one of them as an examp…
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Please consider the following (simplified) testcase:
```VHDL
library ieee;
use ieee.std_logic_1164.all;
entity testcase3 is
generic (
edge : std_logic := '1'
)…
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As of April 22, It seems the exported interface from yosys has changed:
```
jeff@JeffNB:~/work/tools/ghdl-build$ git clone ../ghdlsynth-beta/
Cloning into 'ghdlsynth-beta'...
done.
jeff@JeffNB:~/…
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And here the last two examples from ISE with problems, which are synthesized by `ghdl --synth` but fail with the plugin (same error,): [spmems.zip](https://github.com/ghdl/ghdl-yosys-plugin/files/4516…