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This is not strictly related to CV32E40P as the problem seems to be in fpnew, but did anybody verify the operation of CV32E40P with fpnew in verilator?
There is a coding-style in fpnew, which preve…
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```
./verilate
rv64gc simulating...
%Error: ../testbench/testbench.sv:274:25: Can't find definition of 'EcallFaultM' in dotted variable: 'dut.core.priv.EcallFaultM'
274 | if (dut.core.p…
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Author Name: **Jeremy Bennett** (@jeremybennett)
Original Redmine Issue: 487 from https://www.veripool.org
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Verilog 2001 (and I believe 2005) allows considerable flexibility in short-circ…
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## Observed Behavior
Simulator fails to build with the following output:
```
test@riscv-dev:~/ibex$ fusesoc --cores-root=. run --target=sim --setup --build lowrisc:ibex:ibex_simple_system --RV3…
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Can you attach an example that shows the issue? (Must be openly licensed, ideally in test_regress format.)
```Verilog
`timescale 1ns/1ps
task automatic run();
for (int i=0; i
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Add support for a cross module reference (XMR) operation to a core dialect and to SystemVerilog. The lowering of the core dialect XMR to SystemVerilog is either resolved through:
1. Lowering to Syste…
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modelsim_libs missing in sim/ directory
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### Background Work
- [X] Yes, I searched the [mailing list](https://groups.google.com/forum/#!forum/chipyard)
- [X] Yes, I searched [prior issues](https://github.com/ucb-bar/chipyard/issues)
- [X] Y…
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(Originally posted at Chipyard, being advised to here.)
Bug report
**Chipyard Version and Hash**
Release: 1.9.0
Hash: 7475bfb1a05802ac4dfc3990a889f93164b8d798
**OS Setup**
System 1:
Linux…
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I have found a mismatch between Surelog and other tools in the handling of the RHS expression `'1`.
I haven't found a link to the SV spec, but I did find this relevant page:
https://www.asic-worl…