openhwgroup cv32e40p issues

openhwgroup / cv32e40p

CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform

https://docs.openhwgroup.org/projects/cv32e40p-user-manual/en/latest

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issues

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AXI interface

#1034 AlfredoRodrigues4 closed 5 days ago
1
Floating-Point Performance Bug for FPU_*_LAT>1

#1033 jenniferhellar opened 1 week ago
0
recipe for target 'testbench_verilator' failed (verilator Warning-COMBDLY) - when executing make in cv32e40p/sim/core/Makefile

#1032 Ribisl closed 1 month ago
1
Instruction reencoding documentation

#1031 Guilherme-Soares-Sequeira closed 3 months ago
3
Existed version of cv32e40p pipeline graph

#1030 ahmdotm closed 4 months ago
1
Issue #1027 correction.

#1029 pascalgouedo closed 4 months ago
0
CV32E40P_TRACE_EXECUTION

#1028 nimakolahi opened 4 months ago
13
Not used PULP DIV/SQRT still mentioned in User Manual v1.8.3

#1027 pascalgouedo opened 4 months ago
0
merge dev into master

#1026 davideschiavone closed 4 months ago
0
core-v-docs changed to programs

#1025 pascalgouedo closed 4 months ago
0
All links updated to cv32e40p_v1.8.3 tag for the 3 target repos (core-v-docs, cv32e40p, core-v-verif).

#1024 pascalgouedo closed 4 months ago
0
RTL Code Coverage Hole in cv32e40p_EX_stage module line 237 and 241

#1023 YoannPruvost opened 4 months ago
1
RTL code coverage hole in CV32E40P lzc

#1022 YoannPruvost opened 4 months ago
1
Error during elaboration in xcelium

#1021 vasanth00 closed 4 months ago
2
User Manual final updates.

#1020 pascalgouedo closed 4 months ago
0
RTL Code Coverage Hole in fpnew_divsqrt_th_32 module line 287 and 288 for FPU configuration

#1019 YoannPruvost opened 4 months ago
0
RTL Code Coverage Hole in cv32e40p_EX_stage module line 396 for FPU configuration

#1018 YoannPruvost opened 4 months ago
0
RTL Code Coverage Hole in cv32e40p_EX_stage module line 387 for FPU configuration

#1017 YoannPruvost opened 4 months ago
0
RTL Code Coverage Hole in cv32e40p_EX_stage module line 211 for FPU configuration

#1016 YoannPruvost opened 4 months ago
0
RTL Code Coverage Hole in cv32e40p_ID_stage module line 872

#1015 YoannPruvost opened 4 months ago
0
Up-to-date files for RISC-V ISA Formal Verification.

#1014 pascalgouedo closed 5 months ago
1
Bf16 Accelerator modified RTL

#1013 zeshan-10xe closed 5 months ago
1
RTL Code Coverage Hole in cv32e40p_controller module lines 1241

#1012 YoannPruvost opened 5 months ago
0
RTL Code Coverage Hole in cv32e40p_controller module lines 1187 and 1210

#1011 YoannPruvost opened 5 months ago
0
RTL Code Coverage Hole in cv32e40p_controller module line 850 and lines 852 to 887

#1010 pascalgouedo opened 5 months ago
0
RTL Code Coverage Hole in cv32e40p_controller module line 831

#1009 pascalgouedo opened 5 months ago
0
RISC-V ISA Formal Verification setup and script files for Siemens Questa Processor tool

#1008 pascalgouedo closed 5 months ago
1
RTL Code Coverage Hole in cv32e40p_controller module line 675

#1007 pascalgouedo opened 5 months ago
0
RTL Code Coverage Hole in cv32e40p_controller module lines 632 and 642

#1006 pascalgouedo opened 5 months ago
0
RTL Code Coverage Hole in cv32e40p_controller module line 640

#1005 pascalgouedo opened 5 months ago
0
RTL Code Coverage Hole in cv32e40p_controller module line 399

#1004 pascalgouedo opened 5 months ago
0
jasper SLEC script changes

#1003 mret55 closed 5 months ago
7
Missing area metrics for ASIC synthesis

#1002 thomasdingemanse closed 4 months ago
2
CVFPU RTL updates for implementation tools

#1001 pascalgouedo opened 5 months ago
2
Combinational loops in synthesis (cv32e40px) when adding co-processor through CV-X-IF

#1000 gonzo-sal closed 5 months ago
9
Debug: Which version of OpenOCD

#999 CLappin closed 5 months ago
3
RVFI - Correction corner case conflict on mstatus_fs upades when integer load followed by fpu instr

#998 YoannPruvost closed 5 months ago
0
Adding formal rule for coverage holes on controller

#997 YoannPruvost closed 5 months ago
0
merging dev to master after verifying LEC to v1

#996 davideschiavone closed 5 months ago
0
Reverted PR #993.

#995 pascalgouedo closed 5 months ago
0
Code coverage holes formal analysis

#994 YoannPruvost closed 6 months ago
1
RISC-V ISA Formal Verification files for SiemensEDA OneSpin tool.

#993 pascalgouedo closed 5 months ago
2
User Manual verification section update.

#992 pascalgouedo closed 5 months ago
0
Few lec scripts cleanup and improvements.

#991 pascalgouedo closed 6 months ago
0
Floating Point Unit (FPU) not working

#990 zeshan-10xe closed 6 months ago
1
Update pointer to v1.0.0 coverage reports

#989 MikeOpenHWGroup closed 6 months ago
0
Code coverage report

#988 bekbeis closed 6 months ago
4
Added HWloop CSRs save/restore

#987 pascalgouedo closed 7 months ago
0
Setting correct mstatus fs write mask when csrw to frm and correcting cv.beqimm & cv.bneimm printing in log file

#986 YoannPruvost closed 7 months ago
0
Added illegal instruction exception decoding on unused Imm6 bits for some SIMD instructions.

#985 pascalgouedo closed 7 months ago
0