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Since https://github.com/SymbiFlow/f4pga-arch-defs/pull/2509 was merged, arch-defs packages no longer include `symbiflow_*` tool wrappers used by the makefiles in this repository (https://github.com/c…
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Hi, I'm having trouble using surelog+yosys. You can retrieve my test SV here if you wish to reproduce: https://github.com/bespoke-silicon-group/basejump_stl
I am using the default submodules except…
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Issue was originally titled ` [documentation] chip_integration.md`. Original content follows.
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Greetings.
OpenLane/docs/source/chip_integration.md documentation file in the master branch inc…
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The macro \`default_nettype none is commonly used to cause compilers to throw an error when an undeclared net name is encountered since the tools cannot infer a new net of a given type with this macro…
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[project-f.rst](https://github.com/chipsalliance/f4pga-examples/blob/main/docs/project-f.rst) ([project-f.html](https://f4pga-examples.readthedocs.io/en/latest/project-f.html)) has a bad link in the w…
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Platform option is too ambiguous. Part name should be required to be specified explicitely, then exposed as `part_name` variable so a correct pinmap could be used.
See https://github.com/chipsallia…
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The `symbiflow_route` wrapper needs to determine if VPR met the desired timing, and exit with an error status if it does not. Perhaps we can add an option for skipping the timing check, but the defa…
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After latest changes in synth_ql regarding the BRAM inference got the following issue for qlf_k6n10f family:
BRAM: RegFilePlugin_regFile.0.0.0 ($__RSF_FACTOR_BRAM18_TDP) + RegFilePlugin_regFile.1.0…
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Installing the F4PGA flow and attempting to build the counter example according to the instructions on the pages [here](https://f4pga-examples.readthedocs.io/en/latest/getting.html) and [here](https:/…
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SYMBIFLOW-CLASSROOM-PROJECT
Compiling the included files results in the following error. The design has 2 MMCM's - related to this?
Using original Yosys frontend.
```
(xc7) nelson@CB461-EE1…