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Using the Surelog parser, when initializing an enum, if a width is not set it defaults to one bit.
The bitstream is generated but is faulty.
Works:
```
typedef enum {S_INIT, S_LOOP1,
…
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The `symbiflow_route` wrapper needs to determine if VPR met the desired timing, and exit with an error status if it does not. Perhaps we can add an option for skipping the timing check, but the defa…
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Platform option is too ambiguous. Part name should be required to be specified explicitely, then exposed as `part_name` variable so a correct pinmap could be used.
See https://github.com/chipsallia…
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[project-f.rst](https://github.com/chipsalliance/f4pga-examples/blob/main/docs/project-f.rst) ([project-f.html](https://f4pga-examples.readthedocs.io/en/latest/project-f.html)) has a bad link in the w…
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After latest changes in synth_ql regarding the BRAM inference got the following issue for qlf_k6n10f family:
BRAM: RegFilePlugin_regFile.0.0.0 ($__RSF_FACTOR_BRAM18_TDP) + RegFilePlugin_regFile.1.0…
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# Shift-Ternary Bug
Using Surelog plugin, with Yosys, Yosys gives the following bug
`ERROR: Unsupported expression in mark_as_unsigned!`
Yosys parser is able to compile the program without us…
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The macro \`default_nettype none is commonly used to cause compilers to throw an error when an undeclared net name is encountered since the tools cannot infer a new net of a given type with this macro…
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Installing the F4PGA flow and attempting to build the counter example according to the instructions on the pages [here](https://f4pga-examples.readthedocs.io/en/latest/getting.html) and [here](https:/…
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Hi, I'm having trouble using surelog+yosys. You can retrieve my test SV here if you wish to reproduce: https://github.com/bespoke-silicon-group/basejump_stl
I am using the default submodules except…
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## Issue
If you use `localparam` or `parameter` to initialize parameters, Surelog-yosys plugin throws an error if you initialize it with a string.
The yosys parser is able to correctly interpret th…