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Now, this is a _basic_ sanity check that is driving me insane (pun intended).
Tang Nano 4k. Extremely simple code:
```
module led_water (
input clk,
input rstn,
output reg led_o
…
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**Is your feature request related to a problem? Please describe.**
A clear and concise description of what the problem is. Ex. I'm always frustrated when [...]
**Describe the solution you'd like**…
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Hi Xifan,
I would like to understand how BRAM preload data content is being generated. Hope you can help me to understand that
For example:
1. In the project RTL, we will initialize the BRAM…
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Links:
- [Main project repository](https://github.com/RndMnkIII/Analogizer). The project is described here.
- [Sample project](https://github.com/RndMnkIII/arcade-irem_m92_Analogizer)
- [YC modul…
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**Describe the bug**
When viewing core updates, all of the Jotego cores are suggesting updates from [2ff66e2](https://github.com/jotego/jtcores/commit/2ff66e28b50a027db1a540e2641e94d9ddd71f43) to […
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I am researching clock network architectures of commercial FPGAs for a while and I see FPGAs can have multiple external clock inputs, PLLs, clock gating cells etc.. Also clock networks can be driven f…
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I have extracted the MMLC ROMs from Proteus.exe with the Python script via IDLE and applied the IPS patches, but when I try to run the ROMs via Mesen and agg23's openFPGA core on Analogue Pocket, they…
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The save data size is now handled correctly in v1.0.7. Thanks.
However, I found issues related to saved data.
Game Name
Robopon (HuC-3 mapper)
Analogue OS
v2.0 v2.1
Issues
1. Year and dat…
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**Describe the bug**
A clear and concise description of what the bug is.
Because it can take a very long time, the "Download Pocket Library Images" feature downloads needs an install progress bar.…
ajorg updated
6 months ago
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### Core Author username
AwesomeDolphin
### Core .yml snippet
```yml
display_name: Space Invaders
repository: openFPGA-SpaceInvaders
```