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I was trying to rewire after post placement. I followed below steps to rewire/connect.
- Invoked RW after placement
- removed the EDIFPortInst (edifPortInst) from one EDIFNet(edifNet1) [used a…
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https://www.rapidwright.io/docs/RapidWright_Overview.html#edif-package-logical-netlist similar to this maybe?
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It is clear that after placement in Vivado, the site pins that need to be routed to/from for nets are known after placement and intra-site routing. However, when I import a placed-only design into Rap…
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Although the names of nets, cells, etc. should ideally not contain any slashes, I sometimes have to work with a design that does. Vivado also introduces slashes in net names and cells if you use "-fla…
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Turns out RapidWright is relying on packages that are not fully Java 9 compliant and are using APIs that are deprecated and will no longer be usable in future releases. One example of the packages ca…
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When reading a DCP that contains a submodule with certain characters (including \ and $) in its name, the EDIF Parser fails:
```
java.lang.Exception
at com.xilinx.rapidwright.edif.EDIFParser.exp…
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I am trying to add the 125MHz LVDS clock input of a ZCU104 to my design, however I can't get createIBUFDS to work (nor can I find any examples of how to use it).
The following code produces a `Null…
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I am creating a design where I need to place inverters at very specific LUTs. I was using [Lesson1.java](https://github.com/Xilinx/RapidWright/blob/master/com/xilinx/rapidwright/examples/Lesson1.java…
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SLR names and indices start at 0 at the bottom of the device and move up. Currently, this is the opposite in RapidWright.
This will be corrected in the device model in the next release.
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Hi Chris,
When running the default "Build an IP Integrator Design with Pre-Implemented Blocks" tutorial using both the standalone jar and the auto-installed jar of version 2019.1.2, the process wil…