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Hi,
I have been trying to run the tutorial (the 3 layers example) using various versions of Vivado_HLS.
I used Vivado-HLS 18.2, 18.3 and 19.2 to run the tutorial model. At first, I couldn't pass…
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Sayma s/n -8 worked on bench but in crate reports error when flashing.
```
$ artiq_flash -t sayma --srcbuild ~/artiq-builds/artiq_sayma_20180612_f8627952c8
Design: top;COMPRESS=TRUE;UserID=0XFFF…
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Dear Professor Jiao,
I am currently working on your OpenWiFi project, primarily focusing on CSI extraction. I have encountered a couple of questions:
1. In the CSI extraction process, does it ha…
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After being unable to install on archlinux 64, I have created a fresh install of ubuntu 64 16.04 LTS.
Installation goes OK (except for the utf encoding issues reported elsewhere) but fails at the f…
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Apparently, the proper way to constrain some CDCs (Both AsyncResetSynchronizer and transfer via GreyCounters) should use a max_delay constraint and not a false path.
https://forums.xilinx.com/t5/Vi…
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```shell
mkdir -p synthesis_results_HBM
cp Makefile.synthesis synthesis_results_HBM/Makefile
sed -i 's/xcvu9p-flga2104-2l-e/xcu280-fsvh2892-2L-e/g' synthesis_results_HBM/Makefile
make -C synthesis…
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As part of the work in creating Project U-Ray (based on Project X-Ray) the tooling required by end users (such as FPGA RTL developers) have been split from the repo containing the fuzzers and other do…
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This is to track merging of improved Xilinx Zynq-7000 support.
Current set of changes:
- u-boot SPL: boots the system as in secure mode
- u-boot SPL: has different device tree from u-boot prope…
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### Background Work
- [X] Yes, I searched the [mailing list](https://groups.google.com/forum/#!forum/firesim)
- [X] Yes, I searched [prior issues](https://github.com/firesim/firesim/issues)
- [X] Yes…
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我在官网上下载U50对应的ubuntu22.04的对应bed包，安装好后mpd服务无法正常启动，查看发现是/dev/下没有xfpga设备，该设备是如何生成的？ 我使用lspci | grep Xilinx 能够获取都fpga信息。