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MWE:
```vhdl
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity MWE is
port (
a : in std_logic_vector(0 to 3);
b : in std_logic_vector(0 to 3);
…
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**Description**
Hi Tristan !
Sadly, I don't have a good clean repro-case and simple description here... I'm not even
sure the bug is in GHDL, I might be mistaken here. But here is so far what I f…
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**Description**
"minimum()" is not synthesized
**How to reproduce?**
```vhd :file: issue.vhd
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity bug is
generic…
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I was [verifying GHDL `--synth` and the `ghdl-yosys-plugin` with examples from Xilinx](https://github.com/rodrigomelo9/verifying-foss-hdl-synthesizers). I found a problem with both of them, in an exam…
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**Description**
Currently, synthesis converts falling edge clocks to an inverter and a rising edge clock. While functionally correct, this creates a new clock domain with some skew caused by the inve…
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Hi @rodrigomelo9,
This type of project seems like it would be an excellent addition to the SymbiFlow project. Did you want to join forces here?
The rest of the SymbiFlow project is using the fol…
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ghdlsynth uses the following to compile its interface module:
```
yosys-config --exec --cxx -c --cxxflags -o $@ $<
```
A recent change to yosys breaks the inclusion of rtlil.h... at line 380 it …
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Hi. I am adding GHDL support (the synthesis feature and the ghdl-yosys-plugin) into my project related to support from synthesis to bitstream generation in a vendor-independent way ([PyFPGA](https://g…
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There are a bunch of `Const_*` IDs defined in `ghdlsynt_gates.h` which aren't handled in ghdlsynth-beta:
- [ ] Id_Const_SB32
- [ ] Id_Const_UB64
- [ ] Id_Const_UL64
- [x] Id_Const_X
…
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Hello, my name is Rodrigo and I am starting with ghdlsynth (but I used ghdl for simulation really a lot, since 2006).
I following the link to the Docker Image and I reach a blank page. Is the idea …