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I am implementing a large circuit on OpenFPGA and when in VPR step, it tooks a lot of time (particularly 222590 seconds) to run. In vtr documents, I see that there is a option to optimize my circuit b…
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I am trying to run nextpnr on Alpine Linux. I believe that I have the right packages installed but I am left with the following errors when I run `cmake -DARCH=ice40 .`:
```bash
CMake Warning at …
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Hi,
from what I see in the blif parser, it appears that the .subckt
construct is not supported yet.
I would like this supported because Yosys generated .subckt
commands when the -noflatten option…
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The last release for windows is old, are you dropping support for Windows or is something that's not working ?
By the way, thanks for this amazing job you are doing !
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Hi,
I cant seem to find any error in the Verilog into or out of yosys showing the tow nets it it claims are going to the same sink. They are all competently unique nets going to similar but unique…
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## Steps to reproduce the issue
```
cd examples/python-api/
yosys -m pass.py
read_verilog ../../tests/simple/fiedler-cooley.v
```
## Expected behavior
output of the frequency of modules a…
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I can't get things to compile for the ecp5 architecture.
I am using a recent (last week or so) build of oss-cad-suite to do the synthesis. synthesising fails with the following error message:
`…
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nextpnr-ice40 operates at the logic cell (LUT+FF) level. Investigate the effect of clustering related logic together to take advantage of any local feedback paths (are there any?) and to reduce the pl…
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This example SoC build well with f4pga and Vivado, but does not terminate with default settings:
[https://github.com/chili-chips-ba/openXC7-TetriSaraj.git
29a8501669b167c55efc5da87a8ae7402271d986](h…
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I installed fomu-toolchain-linux_x86_64-v1.5.6 on Ubuntu 20.04 which lacks libffi 6 (7 is the only package in the repos). Working through the workshop I encountered an error building blink.py in the m…