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Defining runname causes dofiles to be executed in batch runs, which may break batch runs. Fix this first and then figure out how to use dofiles with batch runs.
Ping @Roenski
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**Description**
I am using a file to drive some signals on a bus. The files are read into a table and then the table is sent to the bus using a procedure.
In GHDL, I see a different behaviour if the…
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**Description**
If an entity input is of a record type this input cannot be connected to an constant on instantiation of the entity.
Well, it can be connected, but then while starting the simulation…
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For some reason, the Questa simulator does not compile the content of `XmlElement.svh` from SVUnit v3.36.1 due to an unrecognized `get_start_tag_contents` symbol. Reordering functions fixes the issue.…
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In following code one index of the packed array is assigned with continuous assignment, while others are driven by always_ff process
However the error is generated
This behavior is supported in Vi…
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Hi Simon Southwell, I was able to execute the VProc example and had some problems with make run at _verilog/test_ . The log is in attachment. Can you take a look ? there are some error like this :
…
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Verilator runs regression tests, but is about 50x slower than Questa right now. We expect comparable speeds, so there is an issue with something in the cvw coding.
From the sim directory, run veri…
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Issue in running `make apply-patches` as well as `make verilate` in `ara/hardware/` dir.
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Hello sir, I am a newbie in PCIE, I recently want to use cocotbext-pcie to verify the RC->xdma->AXI-MM BRAM datapath, I refer to the testcase in the verilog-pcie, but I only found the connection betwe…
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之前考虑到verilator在业界使用不多，故选择了vcs和questasim，但是这两个对于DPI-C的支持较差，且仿真速度慢，因此考虑重新换回verilator。