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pulp-platform
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ara
The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 core
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[HW] Series fix for corner case bugs
#377
wayne-win
opened
5 hours ago
0
[HW] Refactor the MASKU
#376
mp-17
opened
1 day ago
0
[HW] Iteration_cnt_d should update when result_queue not full
#375
wayne-win
closed
1 day ago
1
[HW] Bump CVA6 to `pulp-v2`
#374
mp-17
opened
2 weeks ago
0
Assistance Needed for Sample Code with GDB Trace
#373
johnodin99
opened
2 weeks ago
0
[HW] Add segment memory instruction support
#372
mp-17
closed
5 days ago
0
[HW] A series of fixes to improve timing
#371
mp-17
closed
2 weeks ago
0
Vector mask instructions VMSBF, VMSIF and VMSOF encountered errors during simulation
#370
0rd1narY1
closed
1 day ago
2
Some Hardware Bug for vstu running imatmul
#369
Rarity0123
opened
4 weeks ago
1
[Readme.md] Fix instructions to flash SD
#368
fulcrum34
closed
3 weeks ago
2
`make checkout` in hardware/ fails
#367
jerryz123
opened
1 month ago
1
How to adding a custom RVV isa on ARA?
#366
js4ngu
opened
1 month ago
2
ara froze while running spmv.
#365
hanyjie
opened
1 month ago
0
Error when make verilate
#364
hanyjie
closed
1 month ago
2
'string.h' file not found when make bin/hello_world
#363
hypertseng
opened
1 month ago
2
Add VCU118 Support to mp/pulp-v1-os-fpga Branch
#362
mrbilandi
closed
1 month ago
3
Stride store has issues.
#361
TimLee-123
opened
1 month ago
0
There is a bug in the store instruction.
#360
TimLee-123
opened
1 month ago
0
I am getting 0 as cycle count when doing the spike simulations
#359
Ajsat3801
opened
2 months ago
2
[hardware] 🐛Fix vasub&vasubu error in simd_alu.
#358
Bowen-0x00
closed
2 months ago
1
Some problem of Vivado
#357
AD738560581
opened
2 months ago
3
[SW] Remove redundant instruction in reset_vector
#356
404allen404
closed
2 months ago
0
There is a bug in the load instruction.
#355
TimLee-123
opened
2 months ago
0
Can we see the hardware usage rate in the simv?
#354
rong-hash
opened
3 months ago
0
[HW] A series of fixes
#353
mp-17
opened
3 months ago
0
[hardware] :bug: Fix alu reduction race condition
#352
mp-17
closed
2 months ago
0
[apps] Multi-precision convolution
#351
mp-17
closed
3 months ago
0
[Bender] Bump common_cells and axi to solve verilation warnings
#350
mp-17
closed
3 months ago
0
[HW] Add hierarchical Verilation
#349
mp-17
closed
3 months ago
0
fst waveform analyzing for imatmul program
#348
Tanishqgithub
opened
3 months ago
0
[HW] Fix CVA6 bug for instructions with side effects
#347
mp-17
closed
3 months ago
0
Additional readme steps
#346
GeertenV
closed
3 months ago
1
Conformal LEC Error: Error: RTL1.13: Mismatched enumeration types are in the assignment
#345
csgxiong
opened
3 months ago
2
new datatypes and precision for conv3d
#344
7undSiebziger
closed
3 months ago
3
[HW] :bug: Fix printf missing characters bug
#343
mp-17
closed
3 months ago
0
[hardware] Fix hanging integer reductions
#342
mp-17
closed
3 months ago
0
Errors in RTL while simulating with Questasim
#341
aitesam961
closed
3 months ago
1
vslideup instruction error
#340
TimLee-123
opened
3 months ago
1
ARA not recognizing Questa Sim Installation
#339
aitesam961
closed
3 months ago
1
[SW] Fix old typos in performance
#338
mp-17
closed
3 months ago
0
llama on ara
#337
grigohas
closed
2 months ago
21
Assembly level Vector Instructions programs for ARA
#336
Tanishqgithub
closed
3 months ago
1
error when I change config to 16 lanes
#335
shkim-emily
closed
3 months ago
5
Any User Specific C program on ARA
#334
Tanishqgithub
opened
4 months ago
2
ARA Synthesis using Cadence or Synopsys Tools
#333
Vinay0203
opened
4 months ago
1
half-precision floating point example code
#332
shkim-emily
closed
3 months ago
1
uint64_t
#331
grigohas
closed
4 months ago
2
riscv-isa-sim
#330
grigohas
closed
4 months ago
0
Add backreferencing for simulation of Cheshire + Ara
#329
moimfeld
closed
4 months ago
0
yaml.h
#328
grigohas
closed
4 months ago
0
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