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pulp-platform
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ara
The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 core
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Stride store has issues.
#361
TimLee-123
opened
1 day ago
0
There is a bug in the store instruction.
#360
TimLee-123
opened
1 day ago
0
I am getting 0 as cycle count when doing the spike simulations
#359
Ajsat3801
opened
3 weeks ago
0
[hardware] 🐛Fix vasub&vasubu error in simd_alu.
#358
Bowen-0x00
closed
3 weeks ago
1
Some problem of Vivado
#357
AD738560581
opened
4 weeks ago
3
[SW] Remove redundant instruction in reset_vector
#356
404allen404
closed
3 weeks ago
0
There is a bug in the load instruction.
#355
TimLee-123
opened
4 weeks ago
0
[HW] A series of fixes
#353
mp-17
opened
1 month ago
0
[hardware] :bug: Fix alu reduction race condition
#352
mp-17
closed
1 month ago
0
[apps] Multi-precision convolution
#351
mp-17
closed
1 month ago
0
[Bender] Bump common_cells and axi to solve verilation warnings
#350
mp-17
closed
1 month ago
0
[HW] Add hierarchical Verilation
#349
mp-17
closed
1 month ago
0
fst waveform analyzing for imatmul program
#348
Tanishqgithub
opened
1 month ago
0
[HW] Fix CVA6 bug for instructions with side effects
#347
mp-17
closed
1 month ago
0
Additional readme steps
#346
GeertenV
closed
1 month ago
1
Conformal LEC Error: Error: RTL1.13: Mismatched enumeration types are in the assignment
#345
csgxiong
opened
1 month ago
2
new datatypes and precision for conv3d
#344
7undSiebziger
closed
1 month ago
3
[HW] :bug: Fix printf missing characters bug
#343
mp-17
closed
1 month ago
0
[hardware] Fix hanging integer reductions
#342
mp-17
closed
1 month ago
0
Errors in RTL while simulating with Questasim
#341
aitesam961
closed
1 month ago
1
vslideup instruction error
#340
TimLee-123
opened
1 month ago
1
ARA not recognizing Questa Sim Installation
#339
aitesam961
closed
1 month ago
1
[SW] Fix old typos in performance
#338
mp-17
closed
2 months ago
0
llama on ara
#337
grigohas
closed
1 week ago
21
Assembly level Vector Instructions programs for ARA
#336
Tanishqgithub
closed
1 month ago
1
error when I change config to 16 lanes
#335
shkim-emily
closed
1 month ago
4
Any User Specific C program on ARA
#334
Tanishqgithub
opened
2 months ago
2
ARA Synthesis using Cadence or Synopsys Tools
#333
Vinay0203
opened
2 months ago
1
half-precision floating point example code
#332
shkim-emily
closed
1 month ago
1
uint64_t
#331
grigohas
closed
2 months ago
2
riscv-isa-sim
#330
grigohas
closed
2 months ago
0
Add backreferencing for simulation of Cheshire + Ara
#329
moimfeld
closed
2 months ago
0
yaml.h
#328
grigohas
closed
2 months ago
0
Question of vwadd instruction
#327
AD738560581
opened
2 months ago
1
[hardware] Fix type of i_addrgen_idx_op_spill_reg
#326
moimfeld
closed
2 months ago
1
Power Consumption for all the benchmarks
#325
Tanishqgithub
closed
1 month ago
1
cva6 with ara on genesys
#324
grigohas
closed
2 months ago
0
Extend backreferencing
#323
moimfeld
closed
2 months ago
1
Non-Compiler based test environment
#322
Tanishqgithub
closed
1 month ago
1
Similar issue as #320
#321
Syedateeb24
opened
2 months ago
2
Failed to execute Ideal Dispatcher mode
#320
Vinay0203
opened
2 months ago
2
[HW/SW] Cheshire integration - Linux on FPGA
#319
mp-17
opened
3 months ago
3
[HW] Refactor and optimize MASKU
#318
mp-17
opened
3 months ago
0
[HW] Make `VLEN` a module parameter
#317
mp-17
closed
3 months ago
0
Failed in RTL Simulation
#316
kevin121121121
opened
3 months ago
1
[apps] Add multi-precision matmul
#315
mp-17
closed
3 months ago
0
Failed in RTL Simulation
#314
Tanishqgithub
opened
3 months ago
25
[HW] 🐛 Fix for floating-point NaN/subnormal handling in opqueues
#313
mp-17
closed
1 month ago
0
[SW] Initial support for compilation in Linux environment
#312
mp-17
opened
3 months ago
0
[HW] Initial support for OS
#311
mp-17
closed
2 months ago
0
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