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pulp-platform
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ara
The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 core
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Question of vwadd instruction
#327
AD738560581
opened
4 months ago
1
[hardware] Fix type of i_addrgen_idx_op_spill_reg
#326
moimfeld
closed
4 months ago
1
Power Consumption for all the benchmarks
#325
Tanishqgithub
closed
3 months ago
1
cva6 with ara on genesys
#324
grigohas
closed
3 months ago
0
Extend backreferencing
#323
moimfeld
closed
4 months ago
1
Non-Compiler based test environment
#322
Tanishqgithub
closed
3 months ago
1
Similar issue as #320
#321
Syedateeb24
opened
4 months ago
2
Failed to execute Ideal Dispatcher mode
#320
Vinay0203
opened
4 months ago
2
[HW/SW] Cheshire integration - Linux on FPGA
#319
mp-17
opened
4 months ago
8
[HW] Refactor and optimize MASKU
#318
mp-17
opened
4 months ago
0
[HW] Make `VLEN` a module parameter
#317
mp-17
closed
4 months ago
0
Failed in RTL Simulation
#316
kevin121121121
opened
5 months ago
1
[apps] Add multi-precision matmul
#315
mp-17
closed
5 months ago
0
Failed in RTL Simulation
#314
Tanishqgithub
opened
5 months ago
25
[HW] 🐛 Fix for floating-point NaN/subnormal handling in opqueues
#313
mp-17
closed
3 months ago
0
[SW] Initial support for compilation in Linux environment
#312
mp-17
closed
1 month ago
1
[HW] Initial support for OS
#311
mp-17
closed
4 months ago
0
similar to #224
#310
Tanishqgithub
closed
4 months ago
1
Executing hello_world Program on Vector Unit and generating it's trace file
#309
Vinay0203
closed
4 months ago
2
[HW] 🐛 Bug fixes
#308
mp-17
closed
5 months ago
0
invalid arch name error
#307
sheikhfaizanqureshi
closed
5 months ago
1
[HW] Bump CVA6 to `pulp-v1`
#306
mp-17
closed
5 months ago
0
RISC-V tests failing
#305
Vinay0203
closed
4 months ago
3
About CVA 6 integrated with vector unit
#304
Vinay0203
closed
5 months ago
1
The tail element does not follow the RVV SPEC requirements.
#303
TimLee-123
opened
6 months ago
1
Running Intel QuestaSim failing with error
#302
magurmach
opened
6 months ago
1
[hardware] disable common-cells assertions forr verilator
#301
mp-17
closed
6 months ago
0
Unclear failure to make toolchain-gcc
#300
magurmach
closed
6 months ago
4
Failing to make verilator
#299
magurmach
closed
6 months ago
1
VID Instruction Error
#298
TimLee-123
opened
6 months ago
1
How to accelerate the verilator compile time?
#297
sodargreen
closed
4 months ago
1
Missing release for v3.0
#296
MarekPikula
opened
7 months ago
0
Simulate fmatmul using 256x256
#295
xieruoyi
closed
8 months ago
2
question of vfredusum
#294
AD738560581
opened
8 months ago
3
VLEN should not be set by preprocessor macro in ara_pkg.sv
#293
jerryz123
closed
4 months ago
2
Understand the details about ara
#292
AD738560581
closed
5 months ago
2
Multi Core Setup Simulation
#291
AdhamRagab25
closed
8 months ago
3
problem with store instruction
#290
AD738560581
opened
8 months ago
0
About Mutilple Vector Core Setup
#289
Rarity0123
closed
8 months ago
7
Inquiring about the arrangement of the VRF (Vector Register File) configuration
#288
TimLee-123
opened
8 months ago
1
[HW] Fix AXI compliance
#287
mp-17
closed
8 months ago
0
VRF address error
#286
TimLee-123
closed
3 months ago
1
verilator simulation error
#285
andrewchi77
opened
9 months ago
3
AXI handshaking logic within the vstu and addrgen violates AXI Specification
#284
T-Szymk
closed
9 months ago
3
div_sqrt_top_mvp.sv proble with VFDIV instruction
#283
AD738560581
closed
8 months ago
1
Rationale of vrf layout design
#282
ckf104
closed
9 months ago
6
Performance Variation on Different Configurations
#281
aaqdas
closed
10 months ago
1
Errors in Verilator Simulation for Test Applications
#280
aaqdas
closed
10 months ago
2
VCD file doesn't cover the signals of the Lanes' submodules?
#279
virturePhenomenon
closed
11 months ago
0
Traces with verilate. Verilate the design is OK but Run the tests faild.
#278
llhe110
closed
11 months ago
2
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