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This issue lays out the Quartz v0.1 MVP version of querying the enclave. It diverged into a longer discussion about long term protocol design for querying, and this longer discussion has been moved to…
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A 16 bit stack machine running eforth on an altera FpgA.
Sadly I cannot figure out what is what. could you please write some documentation?
Chris
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Currently, it does not use them so I need to specify `--ledger-host` and `--ledger-port` explicitly, even if ledger.host and ledger.port are present in daml.yaml
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I don't know if this issue is serious or not, but i suspect it might cause problems.
When i create a function endpoint such as `/test`, the server will respond to all other URLs matching `test` suc…
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Design a circuit that will allow the ESP32 MCU to control the power up sequence of the servo motor controller. The steps in the power-up sequence will (roughly) 1. ESP32 does boot up process, 2. Provi…
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### Is there an existing issue for this feature request?
- [X] I have searched the existing issues
### Is your feature request related to a problem?
There is always an issue with too many potential…
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### Ticket Contents
## Description
An implementer on Avni is someone who configures Avni for an NGO. An NGO is setup as an "organisation" on Avni. The implementer typically works with a dozen dif…
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Hi,
I'm getting started on FPGAs (apologies in advance for noob behavior).
I've bought a Sipeed Tang Primer 20k ( https://wiki.sipeed.com/hardware/en/tang/tang-primer-20k/primer-20k.html ) and I…
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~~**Due date = 10/15/23**~~
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Hi Alastair,
The following gate clock definitions are causing problems in synthesis. This is marked as critical by the _Design Assistant_ task.
Could you fix them, please?
Thank you,
Pepe
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