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I've been thinking long about having some multiplatform (windows and gnu/linux), free (libre), lightweight and standalone tool to analize large bodies of VHDL 2008 code at block/RTL level. That tool w…
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PyHDL sounds very straitforward,it is better to call 'PyHDL' than 'MyHDL',because 'PyHDL' indicates it is a HDL underlying Python
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When I attempted to translate one of my MyHDL designs, I got the following error:
" File "/home/arthur/sim/myhdl/myhdl/conversion/_toVerilog.py", line 1627, in getName
node.signed = _maybeNegat…
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Please answer the following questions.
### Which version of matterbridge are you using?
run ```matterbridge -version```
version: 0.9.3 cd0a2be
### Please describe the actual behavior.
#### …
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code as above graph
when i run it,result as below
, is the problem of global state in simulation instances.
It has been …
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I'm not sure if this is myhdl proper or a thing for rhea ...
What I would like to able to do is interface a running myhdl simulation to the network. Have the exposed objects (serial port, cso, memory…
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I tried coming back to MyHDL after some time away from it, and choose a relatively simple design I tried to write in MyHDL (http://www.latticesemi.com/view_document?document_id=50033): Rotating some L…