cfelton rhea issues - Githubissues

cfelton / rhea

A collection of MyHDL cores and tools for complex digital circuit design

MIT License

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issues

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register file example

#61 hashhsah opened 5 years ago
0
Renamed async to isasync

#60 aorcajo closed 5 years ago
2
spi_slave_fifo_async

#59 mngr0 opened 5 years ago
0
sdram controller

#58 hstarmans opened 7 years ago
1
[enhancement] Provide board definition and blinky example for Red Pitaya

#57 sanojb opened 7 years ago
1
instructions: xula_blinky_host.py on raspberry pi 3B [solved]

#56 hstarmans opened 7 years ago
7
Support Diligent Adept's 'djtgcfg' utility for flow.program() on applicable Diligent boards

#55 NickShaffner opened 7 years ago
1
Remove phantom warnings in verilog conversion related to Xilinx device_clock_mgmt_prim

#54 NickShaffner closed 7 years ago
0
Symbol 'MMCME2_BASE' is not supported in target 'spartan6'.

#53 NickShaffner opened 7 years ago
3
Fix for Issue #41 ISE 14.7 not handling escaped paths on windows 10

#52 NickShaffner closed 7 years ago
0
ClockManagement's 'enable' parameter is not implemented on Xilinx parts

#51 NickShaffner opened 7 years ago
2
ClockManagement's clocks[n] is not driven on Xilinx parts - though ClockManagement's clocksout(n) is.

#50 NickShaffner closed 7 years ago
2
Diligent CmodA7 examples + board definition fix. Fix for issue #50 (clocks[n] is not driven on Xilinx parts)

#49 NickShaffner closed 7 years ago
0
Removing debug prints from xilinx clock management pll calculations.

#48 NickShaffner closed 7 years ago
3
Would be nice if flow.run() provided board information to the top module for things like ClockManagement

#47 NickShaffner opened 7 years ago
2
The vivado path changes and vendor primitive fix.

#46 cfelton closed 7 years ago
1
[enhancement] create a skipif synthesis tool not available

#45 cfelton opened 7 years ago
0
[bug] device_clock_mgmt_prim() will not convert due to using unsupported myhdl features.

#44 NickShaffner closed 7 years ago
7
It would be nice if clocks could generate architecture specific clock tiles as needed.

#43 NickShaffner closed 7 years ago
1
Reworking docs for the rhea system

#42 FelixVi closed 7 years ago
4
Vivido 2016.2 and ISE 14.7 can't process generated .tcl files with absolute paths or spaces on windows 10

#41 NickShaffner closed 7 years ago
6
Initial support for Diligent CModA7 (15T + 35T), Expanded Zybo Definition, Fix Vivado building on windows, Fixed VHDL conversion via rhea.build.toolflow.convert, added Clock.ticks property

#40 NickShaffner closed 7 years ago
19
Adding Numato Waxwing boards

#39 FelixVi closed 7 years ago
2
Added Windows / Mac thumbnail files to .gitignore and final Diligent Anvyl board definitions.

#38 NickShaffner closed 7 years ago
4
Papilio Pro UART example

#37 FelixVi closed 7 years ago
3
A VGA timing fix and additional vga tests and examples.

#36 cfelton closed 7 years ago
1
vga: use the timing parameter class vs. function

#35 cfelton opened 7 years ago
0
Would be nice if Clock() type exposed 'clock ticks' to 'simulation ticks' ratio.

#34 NickShaffner closed 7 years ago
4
Additional port definitions for Digilent Anvyl

#33 NickShaffner closed 7 years ago
1
Papilio One board definition edits

#32 FelixVi closed 7 years ago
1
Added addtional port mappings to Digilent Anvyl board

#31 NickShaffner closed 7 years ago
8
Papilio Pro board definitions

#30 FelixVi closed 7 years ago
2
travis-ci build matrix

#29 cfelton opened 8 years ago
0
"Fixed Conversion Error"

#28 Vikram9866 closed 7 years ago
7
update README.md

#27 Vikram9866 closed 8 years ago
0
Addition of the Altera DE1 SOC board definition and basic examples.

#26 Godtec closed 8 years ago
3
DE1_Soc Pull request

#25 Godtec closed 8 years ago
7
Change GPIO pin assignments to Peripheral based devices vs FPGA based.

#24 Godtec closed 7 years ago
6
Add a digilent basys3 board definition

#23 cfelton opened 8 years ago
0
added support for De1-SoC Terasic FPGA Board.

#22 Godtec closed 8 years ago
1
typo

#21 hstarmans closed 8 years ago
1
Marked slow running tests to skip in py.test

#20 gcc42 closed 8 years ago
9
Outside Interfacing

#19 zignig closed 7 years ago
1
typo

#18 zignig closed 8 years ago
3
Long simulation tests

#17 cfelton closed 8 years ago
2
fix test_emesh_fifo test

#16 cfelton opened 8 years ago
0
Replacing register-file definitions with control-status-objects (cso)

#15 cfelton closed 8 years ago
0
Added more tests for fifo_fast

#14 gcc42 closed 8 years ago
5
Complete the fifo tests

#13 cfelton closed 8 years ago
1
Changed uart to use a single external fifobus interface

#12 gcc42 closed 8 years ago
6