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(Originally filed against jco as https://github.com/bytecodealliance/jco/issues/470).
To reproduce:
```
$ cat test.c
#include
int main() {
puts("hello");
}
$ .../wasi-sdk-22.0/bin/cla…
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I'm working on a project that makes use of these primitives. It does not look to me like they are currently available. What would be involved in adding support for these?
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Hi,
I am trying litex to generate a rocket based soc for terrasic de2 115.
Command i used to build is:
`litex-boards/litex_boards/targets/terasic_de2_115.py --build --cpu-type rocket --cpu-va…
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Hi,
When experimenting with a complete design for board Zybo (Zynq + accelerator), I get a crash in the placer.
Here is the stacktrace:
```
Info: Placed 1 cells based on constraints.
terminat…
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Including these packages in upstream nixpkgs comes with easier access and higher quality assurance.
Continuing discussion from https://github.com/ngi-nix/ngipkgs/issues/7#issuecomment-1748886059,
…
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Code like below, but only for Vivado synthesis seen so far (2019.2, tried a few syn strategy options, didnt help)...
```c
#pragma PART "xc7a100tcsg324-1"
//#pragma PART "5CEBA4F23C8"
//#pragma P…
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Is the HDL source code available and more importantly a complete PCF file? Thanks.
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Does the 10000XX.XX indicate a design issue here (yesterday's icestorm/arachne/yosys pull from github and reinstall), chip ice40UP5k?
Sources: https://github.com/igor-m/UPduino-Mecrisp-Ice-15kB/tree…
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As of a94be4c, the ZeroSoC design barely fits on the iCE40UP5k FPGA I'm using for testing (on an [Icebreaker](https://www.crowdsupply.com/1bitsquared/icebreaker-fpga) dev board). We want to add additi…
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Hi,
I want to configure ice40UP5K's RGB pins as user IOs, similar to what is described in Annex B in TN1288 "iCE40 LED Driver Usage Guide" from lattice and the test code I found on https://github.com…