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Actually more comments (not actually issues) again I can't use the QQ chat to contact the author.
Upgrading PWM refresh rate to reduce color smear:
I have done a simple head to head test compari…
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I'm wondering why Q2 gate is connected to LS_DRV signal. I'd have understood if it was connected to a STM32 GPIO as a way to prevent current flowing in reverse from the battery to the solar panel.
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# Description
There are several way to import and export circuit to and from Qiskit, being OpenQASM2 the most popular one. However, in order to improve interoperability with 3rd parties, we need to…
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**Describe the bug**
Session use 3 nodes located on different areas which makes it hard to track who is using and where its going depend on the ends: (area = country = ISP)
you -> X node in area…
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Engineering should be able to run an update function on a given frequency to:
1. Read the value of all switches
2. Receive data from other programs (Fuel amount, In atmosphere, Master Alarm, etc.)…
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**Issue by [Fatsie](https://github.com/Fatsie)**
_Saturday Nov 16, 2019 at 13:21 GMT_
_Originally opened as https://github.com/m-labs/nmigen/pull/270_
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I am using nmigen for generating RTL to b…
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This project has been idle for a few years, but I have started thinking about it again.
**The situation now**
The basic architecture of this "EVEMS" (electric vehicle energy management system) i…
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### The problem
The switch interlock should use the interlock_wait_time as a means of preventing *any* changes to GPIOs in an interlock group within a certain amount of time since the last change.
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The following security issue just got published: https://github.com/advisories/GHSA-4wm9-3qmv-gvxj
This seems to have been reported actually already month ago. https://github.com/jsonicjs/jsonic/is…
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The SymbiFlow project is slowly getting pretty decent support for the Xilinx Artix 7 part and more specifically the Digilent Arty A7 board. It would be awesome to have a SaxonSoC design in the [SymbiF…