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**Is your feature request related to a problem? Please describe.**
The rule signal_016 requires a signal declaration to be on 1 single line.
In case of simple signals (`std_logic` or alike) this is …
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Hello, I found out in your docs that eventually you would like to add simulation support to slang.
I was wondering what would be the roadmap / directions there? Also, where would you suggest
start…
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The name of the parser: typescript
The tags output you are not satisfied with:
generate ctags like this. and can use it in project
![image](https://user-images.githubusercontent.com/27210994/6050…
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**Describe the bug**
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**Expected behavior**
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**Screenshots**
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**To Reproduce**
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**Version**
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Windows 32 bit
doxygen Release_1_9_3
cmake 3.21
**Stack trace**
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Same as #499 but for variable assignments respectively.
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Hello, first thing congratulate for this awesome work, I just discover this project last weekend and got in love with it.
I am writing this issue because, I discover by accident Silice. I found an in…
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If I want to import a VHDL entity that looks as follows:
```VHDL
entity SomeEntity is
port (input: in std_logic;
output: out std_logic);
end entity;
architecture Behaviour of S…
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Hi all, I am trying to download Morpheus to a Mac, following the instruction from this page: https://morpheus.gitlab.io/faq/installation/macos/
I think successfully installed Homebrew and Morpheus Ta…
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Hello,
first of all, this is more a set of questions rather than a issue with treesitter. These questions came up, when i wanted to write a parser for a language called fusion, that is used as a DSL …
jirgn updated
2 years ago
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### Prerequisites
- [X] I have read [contribution guidelines](https://github.com/vhyrro/neorg/blob/main/docs/CONTRIBUTING.md)
- [X] I am using the latest version of the plugin
- [X] I am using either…