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Hello,
Can you please add support for the [SystemVerilog lexer][1]?
- **hdl** lexer [source][2]
[1]: http://pygments.org/docs/lexers/#pygments.lexers.hdl.SystemVerilogLexer
[2]: https://bit…
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Hello,
Can you please add support for the [SystemVerilog lexer][1]?
- **hdl** lexer [source][2]
[1]: http://pygments.org/docs/lexers/#pygments.lexers.hdl.SystemVerilogLexer
[2]: https://bit…
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** Error: ** while parsing macro expansion: 'TEST_SUITE' starting at D:\\vunit_tb.sv(16)
testbench code:
```verilog
`timescale 1 ns / 1 ps
`include "vunit_defines.svh"
module vunit_test_tb ();…
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Could you give me some advises or guidance to learn about Nyuzi ? THx
kunsa updated
7 years ago
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I tested all three HDL's and only the systemverilog compiler outputs code that gives an error in QuestaSim. The error generated by questasim is as follows:
`** Error: ./Testbench_v1_types.sv (954):…
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Author Name: **Kris Jeon**
Original Redmine Message: 2241 from https://www.veripool.org
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Hi,
I hope to use verilator as a linter +for single file+. So, I want verilator to ignore `includ…
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I'm trying to implement my ChaCha core (https://github.com/secworks/chacha) with Yosys and bumped into one issue. It seems two dimensional arrays defined in local scope is not recognized.
In chacha…
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There are several compromises made to apply skia's BUILD.gn and BUILDCONFIG.gn to the larger Volcano project.
1. Symlinks. Skia's `gn` and `third_party` dirs and Volcano vendor dirs use symlinks du…
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Investigate how to transfer data to the emulator using other methods than SCEMI-Pipes. Suggested alternative is One-Way Callers (OWC).
pear7 updated
8 years ago
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The VUnit Python runner currently support Modelsim but it's designed to support multiple simulators. What other simulators would you like to see supported? Let's have some voting.