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Hello ,
i m a newbie to openrisc system, got an error trying to simulate the de0_nano system.
Reference:
jeebu@jeebu:~/openrisc/orpsoc-build$ fusesoc sim --sim=icarus de0_nano
Compiling /home/jeeb…
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A few additions are needed in order to make it possible to collect code coverage in Modelsim.
- Modelsim specific flag --coverage to enable the features below
- coverage arguments to vcom and vsim
- "…
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Not sure where to report this, but I think I found a compiler bug somewhere in the yosys+arachne-pnr+icestorm toolchain, and I don't know how to go about debugging it.
These two verilog sources, whic…
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I guess I was a bit too optimistic after reading the [Pre-requisites section in the documentation](http://cocotb.readthedocs.org/en/latest/quickstart.html#pre-requisites) which simply mentions
> - Py…
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Recently I spend some time so watch and clean up code in qucs.cpp, the main program. Here is the issue need to be discussed.
Currently qucs support two type of doc: `schematic`, and pure text document…
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Author Name: **Jonathon Donaldson**
Original Redmine Message: 1404 from https://www.veripool.org
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I have a simple video driver design written in SystemVerilog that I'm compiling with veri…
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Author Name: **João Fernandes**
Original Redmine Message: 1098 from https://www.veripool.org
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Hi everyone.
First let me thank the developers for this amazing tool.
Right now i think i a…
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Author Name: **Jason McMullan** (@ezrec)
Original Redmine Issue: 623 from https://www.veripool.org
Original Date: 2013-02-21
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In the following code snippets, while functionally identical, …
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Author Name: **Donald \Paddy\ McCarthy**
Original Redmine Message: 436 from https://www.veripool.org
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Hi, I need the ability to do many simulations each with an injected fault, and I don'…
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Author Name: **Jiang Long**
Original Redmine Message: 440 from https://www.veripool.org
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Hello all,
I am working on a synthesis tool that translate Verilog RTL into netlist. To ensure co…