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Hi,
I'm thinking about adding support for SVA properties to Yosys. However, it is pretty hard to do that without a simulator to test against. So I've tried all the free and free-as-in-free-beer Veril…
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I am currently trying to create a hwpe datamover that transforms the hwpe interface into axi4 streams such that i can use different existing ips directly with PULPissimo. This work is part of an unive…
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Hi,
What does the following FAQ means? Vitis HLS can generate AXI Stream interfaces for an IP according to the standard stream protocol. Why specifically we need a wrapper?
_**### Yes, you can…
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Seems Vexriscv by default has a 'simple' Ibus/Dbus implementation to fetch instructions and read/write data. What are the semantics of this bus? It seems AXI-like, but I cannot really find any details…
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Hello, recently I have been wanting to add an SPI peripheral IP with a standard AXI structure to Briey's AxiCrossBar, which is written in SystemVerilog. I have noticed that the Axi4Shared interface is…
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Thanks for yesterdays live debugging session.
We found our mistake in the usage of Axi4Manager and Axi4Memory.
The frequency of the OSVVM verification components was not matching the period of o…
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Hello! I'm glad to see more interesting experiments!
I saw you posted a link to [Xilinx DMA PCIe Tutorial](https://www.linkedin.com/pulse/xilinx-dma-pcie-tutorial-part-1-roy-messinger) by Roy Messing…
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Hello, how could I use your schematic viewer to visualize diagrams of VHDL/Verilog hierarchical entities starting from source files?
Thank you and congratulations on your project.
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cocotb==1.6.2
cocotbext-axi==0.1.16
Questa Sim-64 Version 10.7f
Hello,
I am instantiate AXI-S driver like this:
self.axi4_s_drv = AxiStreamSource(AxiStreamBus.from_entity(self.dut.axi_s_if), …
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From the vhdmmio general documentation:
> vhdmmio concerns itself with the generation of register files. To vhdmmio, a register file is an AXI4-lite slave, consisting of any number of fields, occup…
m-kru updated
2 months ago