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The objective would be to use compressed bounds within CHERI to get the BASE (TOP) and LIMIT(BOTTOM) of the virtual or physical address space.
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A bit in `Xenvcfg` has recently been allocated in the CHERI spec to enable/disable CHERI at different privilege levels. Looking at https://github.com/CTSRD-CHERI/cheri-specification/issues/69 I think …
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This a placeholder to note that the pointer masking extensions (which are mandatory in RVA23) `Smmjpm`, `Smnjpm` and `Ssnjpm`, need to be analysed in the presence of CHERI.
https://github.com/risc…
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Other RISC-V extensions which add state to the machine (F and V) each have two bits allocated in `mstatus/sstatus` for lazy context save/restore, and also to restrict access to the new state.
To be…
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Running with a kernel/userlevel from #2080, I saw this kernel panic when starting an aarch64 Chromium web browser within an otherwise entirely purecap (kernel, userlevel, desktop) environment:
```p…
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We currently do not support Special Capability Register (SCR) testing. When looking at the RISC-V TG draft specification, it seems SCRs are soon under the "CSR hood". Until the TG specification is rat…
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Morello LLVM now passes varargs and memargs via a buffer pointed to by a capability register (https://git.morello-project.org/morello/llvm-project/-/merge_requests/204). This is needed for library-bas…
dpgao updated
2 months ago
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As per https://github.com/microsoft/cheriot-sail/issues/56 recent dev versions of Sail have started to give an odd type check failure compiling the CHERIoT sail model. It looks like this might be comm…
rmn30 updated
2 months ago
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This issue is part of the Strict Provenance Experiment - https://github.com/rust-lang/rust/issues/95228
I left a few little ` FIXME(strict_provenance_magic)` comments around core::ptr to indicate p…
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https://github.com/rems-project/cerberus/commit/20d9d5ce2e982c4744ef6911a25a3be9307518f3 fixed the existing CN lemma tests, but these should really be part of the CI. This requires re-working the CI s…