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I have started to work on a better version for my type-based waveform viewer for [Tydi](https://github.com/ccromjongh/Tydi-Chisel) and Chisel-related projects (Tywaves).
My chisel fork: https://git…
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目前Chisel/FIRRTL社区比较冷清
我提议是对RocketChip进行拆包后,添加文档测试,学习LLVM的优良传统,确定依赖,添加文档,可以upstream的upstream,不能的部分,自己作为Upstream进行持续维护,目前我正在推进多个工具进标准库:
1. Clock-domain-crossing
- AsyncQueue: architecture, verifica…
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FIRRTL output would allow BSV to take advantage of the ecosystem popping up around Chipyard/RocketChip while still using BSV.
FIRRTL: https://www.chisel-lang.org/firrtl/
Thoughts?
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Hi, I'm just starting to test out chiffre and I was trying to setup the sample LeChiffre configuration. I ended up having to change the patch file, but now I am getting this error and I don't have an…
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Adding `fopen` and `fclose` allows `fwrite` to real files instead of just standard streams.
According to SV spec 21.3.1, the return value `fd` of `fopen` is an `integer`. The CIRCT SV dialect does …
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I'm not sure if this is a bug. If a constant e.g. `channelId` propagating to DPI function, it will be eliminated. I'm currently using a `dontTouch` to work around, but I think this should be resolved …
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When attempting to inject faults into a (ground) member of an aggregate type, FIRRTL reports an error during one of its passes. For example, if I try to inject an error into the program counter of Ro…
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While the [documentation](https://mlir.llvm.org/getting_started/Debugging/#detecting-invalid-api-usage) states that there might be false positives, I think it might be worth a look into the individual…
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I created a new tracing interface which allows me to pipe out additional informations out of the simulation. I've created this interface exactly like TracerV, but a little bit simpler as it is just tr…