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Hi, I'm just starting to test out chiffre and I was trying to setup the sample LeChiffre configuration. I ended up having to change the patch file, but now I am getting this error and I don't have an…
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I use the following codes to generate verilog using this repository as template:
```scala
object myMultipierMain extends App {
val path = "~/project/CPU/playground/generated"
val firtoolOption…
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When attempting to inject faults into a (ground) member of an aggregate type, FIRRTL reports an error during one of its passes. For example, if I try to inject an error into the program counter of Ro…
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目前Chisel/FIRRTL社区比较冷清
我提议是对RocketChip进行拆包后，添加文档测试，学习LLVM的优良传统，确定依赖，添加文档，可以upstream的upstream，不能的部分，自己作为Upstream进行持续维护，目前我正在推进多个工具进标准库：
1. Clock-domain-crossing
- AsyncQueue: architecture, verifica…
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FIRRTL output would allow BSV to take advantage of the ecosystem popping up around Chipyard/RocketChip while still using BSV.
FIRRTL: https://www.chisel-lang.org/firrtl/
Thoughts?
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### Before start
- [X] I have read the [XiangShan Documents](https://xiangshan-doc.readthedocs.io/zh_CN/latest). 我已经阅读过香山文档。
- [X] I have searched the previous issues and did not find anything releva…
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I created a new tracing interface which allows me to pipe out additional informations out of the simulation. I've created this interface exactly like TracerV, but a little bit simpler as it is just tr…
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Input:
```firrtl
FIRRTL version 4.0.0
circuit ConstFlip :
extmodule Sink :
input x : const UInt
public module ConstFlip :
output out : { x : const { flip y : UInt } }
ins…
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### Background Work
- [X] Yes, I searched the [mailing list](https://groups.google.com/forum/#!forum/chipyard)
- [X] Yes, I searched [prior issues](https://github.com/ucb-bar/chipyard/issues)
- [X] Y…