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Currently, we have a couple of purely structural Verilog files in OpTiMSoC: the toplevel files at various levels of the hierarchy. Creating these files is tedious and error-prone (getting wiring wrong…
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I am working on the remote file translator, specifically on IP-XACT currently. I don't see a way to model some of the address block attributes such as `range` and `width`.
~~~xml
…
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For exemple, Xilinx and Altera have their own file format to specify mapping between design pins and package pins (+ specify pin technologies, current, terminaison, ...)
It could be great to have a s…
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@SiFive and @drom have created a thing called [DUH](https://github.com/sifive/duh). This format describes things like wishbone busses and stuff.
This seems like a good thing to integrate with FuseS…
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Currently the hierarchy in librecores ends with "projects", which can be HW or SW or combined works.
We should introduce "IP Cores" (or named similarly) as a subhierarchy below a project (1:n).
Desi…
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Hi,
I started to use open5gs recently and now my small cell already can register open5gs **with IPv6**.
But when I try to use usim on my LTE cpe, I always can't get the network service.
Did anyth…
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### Description
I'm attempting to get Siemens property-checker running.
My first step would be to see what commands are being executed to run Jasper Gold
util/dvsim/dvsim.py /opentitan_org/hw/top…
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Since master/slave is defined as an empty tag like this (see also http://www.accellera.org/XMLSchema/SPIRIT/1685-2009/busInterface.xsd) :
```
...
```
in the current implementat…
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Hello everyone,
As someone who has almost no background in digital electronics a more detailed guide (or perhaps a walkthrough using one of the example codes) on how to implement the generated NNge…
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The IP-XACT standard allows for an optional mask element inside a field reset element. This is used to define which bits of the field have a known reset value. The absence of the mask element makes th…