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In your documentation I've seen you import in these 2 ways:
```python
>>> from migen.fhdl.std import *
or
>>> from migen.fhdl import *
```
However, when I try to do run this command:
```
>>>…
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I wrote a Migen code which used MultiReg for signal synchronization across clock domains and the relevant section is similar to the test code below:
```python
from migen import *
from migen.fhdl …
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When attempting to use Record.raw_bits() to create a bus to manipulate in further Migen expressions, Migen will generate the concatenation "in place" in the generated Verilog code for each use of the …
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https://irclog.whitequark.org/m-labs/2017-06-09#1496995548-1497020136;
https://github.com/m-labs/migen/blob/master/migen/sim/core.py#L308
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Being able to install migen through PyPi would be a useful for stable configurations. It would also increase the exposure of migen to more of the Python community.
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I am a beginner in HDL and migen seems like a great option as I already know python well and it seems like migen would let me design hardware without having to learn a new language! (thank you)
ho…
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I would like to split the build process of a design on two hosts:
- the first host would call `platform.build(run=False)` and create a build folder with the files required for a build
- that folder …
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As discussed in m-labs/migen#180, the pinout and schematics indicate the serial wire names from the µC perspective. Should at least the netlist be changed to reflect the FPGA perspective?
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I'd like to be able to translate the migen Module hierarchy into the exported HDL hierarchy at least to some extent.
* This would allow estimating resource usage at some useful granularity.
* It w…
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* Migen -> nMigen2 (There are too many improvements to list here, see the various nMigen discussions. For example, on a very practical level, this should take care of issues like https://github.com/m-…