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Hi everyone, I am a newbie in Chisel.
Does anyone has experience in that case, please help me?
Thank you so much for any kind helps.
My goal is to add a instruction detecting signal (in particula…
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open the "enableCommitMapTable" then error occurs when run:
```
./emulator-rocketchip-BOOMConfig +max-cycles=100000000 +verbose output/rv64ud-v-move 3>&1 1>&2 2>&3 | /home/hanzhipeng/riscv-toolchai…
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I am trying to mount a Rocket core on a zcu104.
So I tried to use this repository for development.
I have completed the generation of the verilog file, but when creating the bitstream, I get an erro…
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I'm in Branch `bump-stuff`.
I can successfully add [Inclusive cache](https://github.com/sifive/block-inclusivecache-sifive) to Rocket-Chip by adding this to `system/Configs.scala`.
```scala
cla…
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**Type of issue**: bug report
**Impact**: unknown
**Development Phase**: request
**Other information**
https://github.com/riscv-boom/riscv-boom/issues/659 seems related.c
https:…
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It would be better if the xvisor can have support for sifive drivers, such as sifive-spi/serial/gpio. Since h-extention has been merged into rocketchip, we can run xvisor on the rocketchip.
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import dsptools.tester.MemMasterModel
import freechips.rocketchip.amba.axi4
abstract class FIRBlockTester[D, U, EO, EI, B new AXI4FIRBlockTester(lm) }
here is the error:
cmd8.sc:5: not …
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If you have `ROCKETCHIP_ADDONS` (SBT unmanaged source directories) I can't seem to build the project using wake. Specifically, if the Rocket Chip sources are modified to require files inside…
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I believe the current status of the CI (for sel4test at least) is that not all platforms that claim to be supported are tested. Obviously we cannot buy all the hardware to actually run the tests, but …
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Hello seldridge,
1) I built Dana+Rocket flow successfully for both emulator and FPGA. When I run dana/smoke test, all of them failed for unknown reasons to me. Below are logs that I got after runni…