bu-icsg dana issues - Githubissues

bu-icsg / dana

Dynamically Allocated Neural Network Accelerator for the RISC-V Rocket Microprocessor in Chisel

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issues

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when generating boot.bin for zedboard

#61 xiyurain opened 4 years ago
0
Update README.md

#60 HaFred closed 4 years ago
0
GZIP error when use the emulator

#59 CristinaZN closed 4 years ago
0
make project ROCKETCHIP_ADDONS=dana CONFIG=DanaZedboardConfig with error

#58 nicolast0604 opened 4 years ago
0
bare metal dana

#57 nicolast0604 opened 4 years ago
1
VTestHarness.mk:69: recipe for target 'SimDTM.o' failed

#56 nicolast0604 opened 4 years ago
2
VTestHarness.mk:69: recipe for target 'SimDTM.o' failed

#55 nicolast0604 closed 4 years ago
1
error for make in dana

#54 nicolast0604 opened 4 years ago
0
XFiles.scala:12: not found: object perfect

#53 nicolast0604 opened 4 years ago
1
The emulator program gets into a dead circle

#52 likmin opened 5 years ago
0
RRArbiter Unconnected X Generation

#51 seldridge opened 5 years ago
0
Get smoke tests running again

#50 seldridge closed 6 years ago
0
Errors for dana/smoke test

#49 hoangt opened 6 years ago
2
Compilation error with dana emulator

#48 kevinyuan opened 6 years ago
9
Error in building emulator

#47 phthinh closed 6 years ago
1
README.md Updates

#46 seldridge opened 6 years ago
0
Binary Configuration uses 32-bit Pointers, ABI cleanup

#45 seldridge closed 6 years ago
1
Refactor SRAM to use `SeqMem`

#44 seldridge closed 6 years ago
0
Use Read Enables on all SRAMs

#43 seldridge closed 6 years ago
0
Parse learn trace

#42 matejaputic opened 7 years ago
0
IBM Initial Open Source Sync

#41 seldridge closed 7 years ago
1
pls help where to buy fpga

#40 Sandy4321 closed 7 years ago
1
Add PACT citation and thesis link

#39 seldridge closed 7 years ago
0
add comments about FPGA configurations

#38 zuasia closed 7 years ago
3
Re-sync with rocket-chip master, move to Chisel 3

#37 seldridge closed 7 years ago
0
At run-time, selectively ignore "small" operations

#36 seldridge opened 7 years ago
0
Refactor Control Module

#35 seldridge opened 8 years ago
0
Issue 17 utl interface

#34 seldridge closed 8 years ago
0
Remove multicore support

#33 seldridge closed 8 years ago
0
Enable Supervisor Access to X-FILES/DANA

#32 seldridge closed 8 years ago
0
Enable use of X-FILES/DANA and DebugUnit from the Kernel

#31 seldridge closed 8 years ago
0
Add dana-benchmark, multi-transaction bug fixes

#30 seldridge closed 8 years ago
0
Wrap TID at 2^(tidWidth-1)-1

#29 seldridge closed 8 years ago
0
Single input networks dying at epoch 128

#28 seldridge closed 8 years ago
1
Unexpectedly Poor Performance on Large FPGA Configuration

#27 seldridge opened 8 years ago
0
Add support for interrupts

#26 seldridge closed 8 years ago
0
Build Errors (riscv-tests, python 2.6?)

#25 zaddan closed 8 years ago
9
logic error

#24 zaddan closed 8 years ago
2
Intermittent xorSigmoidSymmetricPair Failure

#23 seldridge opened 8 years ago
2
Enable testing without rocket-chip

#22 seldridge opened 8 years ago
0
Separate X-FILES and DANA, DANA now a backend

#21 seldridge closed 8 years ago
0
Bump FANN to upstream, disable OMP RISC-V builds

#20 seldridge closed 8 years ago
0
Extend fann-xfiles with support for cross validation and mini-batches

#19 seldridge opened 8 years ago
0
fann-xfiles refactor

#18 seldridge closed 8 years ago
0
Use UTL to load/store NN configurations

#17 seldridge closed 7 years ago
2
Correct bad Register File address computations

#16 seldridge closed 8 years ago
0
Add Checking that Neural Network Configuration Format is Valid

#15 seldridge closed 8 years ago
0
Assertion Failure for Pe8 Epb16 Config on xor-sigmoid-128o

#14 seldridge closed 8 years ago
2
Respond when no ASID, add X-FILES/DANA ID

#13 seldridge closed 8 years ago
0
Enable support for Travis-CI, Overhaul Makefiles

#12 seldridge closed 8 years ago
0