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### Background Work
- [X] Yes, I searched the [mailing list](https://groups.google.com/forum/#!forum/chipyard)
- [X] Yes, I searched [prior issues](https://github.com/ucb-bar/chipyard/issues)
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This sim seems to run fine if I don't dump the fst, but when I do I get this crash. I'm using `--dump-arrays` if it matters.
```
nvc: ../src/rt/wave.c:493: fst_get_ptr: Assertion `l->nparts == ty…
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Sorry for the long issue, I'm trying to provide as much context as possible.
TL;DR: When trying to elaborate a model tree, registers with sequential fields are reported to have a bigger size, resulti…
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I have a grammar of Python3 (from the antlr4 grammar repository), extended with query language constructs. The grammar file is here: [Grammar file](https://github.com/pavelvelikhov/pythonql/blob/maste…
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### Description
`typst 0.11.1 (50115102)`
I am not sure if the source of the bug is in the typst compiler or in the https://github.com/andreasKroepelin/polylux package.
```typ
#import "@previe…
m-kru updated
5 months ago
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Basic idea is to create something low-level, like LLVM Bitcode or WebAssembly, to create the HDL compilers emit the code in this format, which will be fed to the routers/synthesizers after. This will …
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This is an inquiry to the wider audience who are working on getting NVDLA running on a FPGA platform--we'd like to share what we are doing and check progress on other groups out there .
we are putt…
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https://github.com/SystemRDL/systemrdl-compiler/blob/f9fc64029f1337cb30e984c84a15f07d8d842ea3/docs/dev_notes/inferred_placement.rst?plain=1#L83C1-L83C25
The default behaviour of the tool is to plac…
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Presently there's no way (I think?) of asking an address map to give you all the registers (or memories or sub address maps) within it.
I think in the same way that registers have the `readable_field…
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Hey guys.
We are using cocotb 1.8 and also tried 1.8.1 on previous versions of vcs [ up to T versions ] we can load our environment and use cocotb. we are having a blast.
However when we try ve…