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Hi cloning this repo as is (https://github.com/Minres/TGC-VP.git) works fine as intended though,
however, if we try to fork this repo (e.g. like in VP-Vibes repo) and then try to clone
```
$ git c…
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Hi, I hope you are well. I am facing the following error while regenerating the verilog files in the src_SSITH_P2 folder with `make compile` command:
```
compiling ../src_Core/Near_Mem_VM_WB_L1_L2…
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**The name of the parser:**
SystemVerilog
**The command line you used to run ctags:**
```
ctags-universal --options=NONE --sort=no -f - --fields=Kzn --pattern-length-limit=0 ctags_uni_issu…
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Hello !
After I git clone it,I execute the script "./setup_submodules.sh" in the root directory.When I do "make",it has errors.Details as follows:
[gzl@gzl tnoc]$ cd sim
[gzl@gzl sim]$ ls…
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Not sure if this is a bug, intended behavior, or just me doing something wrong. My goal is to have multiple telemetry definitions with the same general format but differing by a single ID_ITEM, and o…
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I installed the riscv-gnu-toolchain using this config because I want to be able to do compiles for an RV32i cpu I'm designing in RTL System Verilog:
./configure --prefix=/opt/riscv --enable-multili…
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Hi Andrea
The python script to flush the S3 cache for ch.swisstopo.swisstlm3d-karte-farbe.3d and ch.swisstopo.swisstlm3d-karte-grau.3d initially developed by @loicgasser throws an error
Result:…
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**Description**
Running `docker stack deploy --prune -c docker-compose.yml ''` (the empty name can be done on purpose by using empty quotes or by mistake by passing a empty string as a command li…
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again and again it does this file saves ok and then will NOT come back up and i spend hours and hours then to have the file not load says xml parsing error. Then why did it save it ! Can you please fi…