bluespec Flute issues - Githubissues

bluespec / Flute

RISC-V CPU, simple 5-stage in-order pipeline, for low-end applications needing MMUs and some performance

Apache License 2.0

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issues

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Halting behaviour

#43 michalmonday opened 4 weeks ago
1
Questions about some errors when running simulation or tests

#42 ingmarfjolla opened 9 months ago
2
Compressed hints should be legal

#41 PeterRugg opened 1 year ago
1
make compile fail (CPU.bsv line 319)

#40 michalmonday closed 2 years ago
1
Add unit test for AXI4_Fabric

#39 darius-bluespec closed 2 years ago
0
UART address unsupported while communicating between the flute core and uart ip through AXI4 bus

#38 dipal004 closed 2 years ago
3
use HTTPS urls for submodules instead of SSH so people can clone the …

#37 kenta2 closed 2 years ago
0
Flute on GaloisInc/BESSPIN-GFE

#36 rgollap1 opened 3 years ago
0
Modify JTAG settings for different boards

#35 LeonardooAlves opened 3 years ago
0
Error while regenerating SSITH P2 verilog files

#34 LeonardooAlves closed 3 years ago
11
PLIC: Allow multiple interrupts to be claimed but not completed

#33 jrtc27 closed 3 years ago
0
Adjust RISC-V extension naming convension

#32 zeeshanrafique23 closed 3 years ago
0
RoundMode in ISA_Decls conflicts with that in FloatingPoint.bsv

#31 jonwoodruff opened 3 years ago
1
Near_Mem_TCM is missing

#30 davidchisnall opened 4 years ago
0
Optimise some adders in CPU_Fetch_C

#29 ivanmgribeiro opened 4 years ago
0
Abstract over the cache-word size in the write through cache

#28 gameboo closed 4 years ago
0
FPGA Synthesis

#27 kullkullzed closed 4 years ago
0
mkBuild_Dir.py: Update for new FDIV/FSQRT macros

#26 jrtc27 closed 4 years ago
0
Provide an optional AXI4-Lite slave for coherent DMA

#25 jrtc27 closed 4 years ago
2
AXI4_Deburster.bsv: Make implementation reasonably synthesisable

#24 jrtc27 closed 4 years ago
0
plic-test compile and sim fail

#23 neelgala opened 4 years ago
0
找不到顶层文件

#22 Verdvana closed 4 years ago
3
CPU: Further fix single-step logic in the presence of branch mispredictions

#21 jrtc27 closed 4 years ago
2
MMU_Cache: Only update State_and_CTag_CSet once we know there is no error

#20 jrtc27 closed 4 years ago
1
CPU: Debug Module Interaction Fixes

#19 jrtc27 closed 4 years ago
0
Only update way_hit when there is an actual hit at this way.

#18 jonwoodruff closed 4 years ago
3
Doc/Microarchitecture/Microarchitecture.tex: minor typo fixes

#17 gktrk closed 4 years ago
1
Bug fix: NaN checks on output of FP compute pipelines

#16 nirajnsharma closed 4 years ago
0
Fixed default verbosity for FBox_Top to 0

#15 nirajnsharma closed 4 years ago
0
F/D modifications and TV support for F/D

#14 nirajnsharma closed 4 years ago
0
Separation of FP datapath and TV support for FP

#13 nirajnsharma closed 4 years ago
1
Reduce mispredict penalty by one cycle

#12 jrtc27 closed 4 years ago
0
Fix fall-through PC for branch predictor miss with RVC instruction

#11 jrtc27 closed 4 years ago
0
Fix tandem verification trace for non-floating point configs

#10 cahz closed 5 years ago
1
Where Can I get the Bluespec systemverilog compiler?

#9 hyf6661669 closed 5 years ago
1
Moved IFetch on Traps to a later stage

#8 nirajnsharma closed 5 years ago
0
Enabling FP Divide

#7 nirajnsharma closed 5 years ago
0
FBox modifications. MSTATUS.FS fix.

#6 nirajnsharma closed 5 years ago
0
Verification / Test Coverage

#5 ben-marshall opened 5 years ago
0
FBox bug fixes

#4 nirajnsharma closed 5 years ago
0
Include_RV32IMU.mk: No such file or directory

#3 GiuseppeDiGuglielmo closed 5 years ago
1
FBox Integration

#2 nirajnsharma closed 5 years ago
0
Add a file that was missing from an earlier commit (TV 2.0 sync-up with Piccolo)

#1 quark17 closed 5 years ago
0