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A number of fuzzers (and associated minitests) work on Vivado 2017.2 but are broken on Vivado 2017.3. A quick analysis shows its related to MUXF8.
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### Background Work
- [X] Yes, I searched the [mailing list](https://groups.google.com/forum/#!forum/firesim)
- [X] Yes, I searched [prior issues](https://github.com/firesim/firesim/issues)
- [X] Yes…
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There are quite a few Ethernet MAC cores, but mostly in Verilog. I've a project written in VHDL, use GHDL, and therefore looked for a core written in VHDL, and found this project.
The core was tested…
wfjm updated
3 months ago
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Hello, I encountered the P4 IP error ( similar to Issue #22 ) when running `vivado -mode batch -source gen_vivado_ip.tcl -tclargs -board_repo $BOARD_REPO`. I used `export VitisNetP4_Option_VISIBLE=tru…
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Hello,
I found a build error in the RHEL8 environment(pull is Ok).
$sudo docker build -f docker/Dockerfile.vivado -t ghcr.io/fastmachinelearning/hls4ml-tutorial/hls4ml-0.7.1-vivado-2019.2:latest .…
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if using the cheby-generated AXI4-Lite interface in Vivado block design without a wrapper following issues arise:
* the naming of the interface does not follow usual scheme of `[MS]_AXI_NAME`, inst…
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I'm trying to get an artyboard a7 working; it shows up in lsusb as having the compatible device (vendor 0x0403, product 0x6010). xvcd starts up okay, doesn't complain about missing devices, and patien…
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We are using the vivado 2019.1 linux version lab edition
[Vivado 2019.1: Lab Edition - Linux] filename=Xilinx_Vivado_Lab_Lin_2019.1_0524_1430.tar.gz)
but it has no specific VIVADO_HLS. and we g…
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hello i'm new to using docker i'v downloaded the without vivado version and now i want access vivado in my host machine to synthesis the code !!!! is it possible ? i mean how should we change this lin…