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Hi,
i am trying to run keystone on an Alveo 250 FPGA using Chipyard and Firesim. When I execute the workload, the boot hangs after `[ 0.249572] Serial: 8250/16550 driver, 4 ports, IRQ sharing di…
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Hi,
I am building a microcontroller based on Ariane and I am reusing a lot of the peripheral I was able to find here.
I implemented the system on FPGA (zcu102 board) and I connected the RISCV-base…
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Hello,
Amazing work with this usb core. Is it possible to use it directly as a USB-UART bridge? Like D+ and D- entering the FPGA and (UART) TX & RX leaving via output pins
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Dear friend, you have done a great job.
Thank you for that.
I would really like to know why it is possible to generate the maximum 375 kHz?
And this is at a FPga frequency of 50 MHz.
I tried to se…
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Hello there! I'm want to say a few words about NAND chip replacing. Get a look onto NAND controller, in 1G it's external with ATA interface to the main SoC. Chip support of this controller is very dec…
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I want to add a new slave peripheral to Riscv, and I took SRAM as reference to know the modules and packages that I should modify, and I found that I should add:-
1) Index, start and end address in t…
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I need support for Project Mistral for my chameleon96 and Terasic Sockit Altera Cyclone V boards
A blinky example done with project mistral is done here https://github.com/kprasadvnsi/mistral-CV96-bl…
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Dear LiteX devs.
I enjoy LiteX very much, great work great concept! Hope I can help.
### Background:
Yesterday I naively experimented a bit with Litex - platformio - zephyr(rtos). The idea was …
hvegh updated
3 years ago
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Hello, my application scenario requires a DDR3 controller with axi interface, so I generated my DDR3 source code based on the stlv7325 development board. However, even if DDR3 initialization is succes…
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**Description**
I recently tried to compile the kernel on the Alpine Linux, however it failed to pass the insn_decoder_test with the following message:
```
arch/x86/tools/insn_decoder_test: error: …