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I need support for Project Mistral for my chameleon96 and Terasic Sockit Altera Cyclone V boards
A blinky example done with project mistral is done here https://github.com/kprasadvnsi/mistral-CV96-bl…
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Generation of bit stream.
` litex-boards/litex_boards/targets/xilinx_ac701.py --build --cpu-type rocket --cpu-variant linux4 --sys-clk-freq 50e6 --with-ethernet`
--> Bitstream generated successfully…
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I'm trying to use `openFPGALoader` with an [Arrow DECA](https://www.arrow.com/en/products/deca/arrow-development-tools) development board. Its product page claims it has a USB-Blaster II included, so …
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I would like to compile my SV code with yosys+UHDM, I followed the instructions from here:
https://antmicro.com/blog/2022/02/simplifying-open-source-sv-synthesis-with-the-yosys-uhdm-plugin/
except I…
jeras updated
2 years ago
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Hey guys!
I dont have a de10soc , but i have a de1soc(board).
I would like to know if anyone has tried to implement this fantastic work in it.
Do you think it is possible to implement on the de1soc…
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Since the topic comes up frequently and I couldn't find a place to tack this onto, here is an unsorted collection of things we noticed while considering moving away from EEM towards DIOT crates.
Pr…
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Open On-Chip Debugger 0.11.0+dev-04033-g058dfa50d (2023-02-20-09:48)
Licensed under GNU GPL v2
For bug reports, read
http://openocd.org/doc/doxygen/bugs.html
/home/wjc/Desktop/VexRiscv_old/cpu0.y…
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I would like to simulate USB devices on the ATSAMD21, up to the point that I can hook the model up to USB/IP and use it from the host. In particular, I'm interested in simulating USB HID devices, but …
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I was building this for my SteamDeck and noticed that during compiling, it was building things like drivers for Wifi Chipsets the Steamdeck doesn't have, as well as things like Nouveau.
Would it ma…
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The README file mentions the following:
```
3. Check out /examples/versa_ecp5_udp_loopback for a good practical example of how to get
started with the Liteeth core solo in an FPGA.
```
I've t…