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demo_gpio_irq uses firq channel 8. The following changes are needed in main.c to make it work:
//install_err += neorv32_rte_exception_install(RTE_TRAP_FIRQ_1, gpio_pin_change_irq_handler);
insta…
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Rather than a feature request, this is a topic for discussion. It seems that [riscv/riscv-arch-test](https://github.com/riscv/riscv-arch-test) might be handled as a submodule in subdir `riscv-arch-tes…
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I tried running the script ghdl_sim.sh on Ubuntu (WSL 18.04) and it gave and error about --max-sstacck-alloc=0' so I tried running it with that option and it output this message after running starting…
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**Describe the bug**
I tried to reproduce the project from the description in Vivado 2019.1, but got parameter type conversion errors:
`[IP_Flow 19-1837] Failed to convert long value '0' to HDL valu…
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It would be great if the UART ports supported HW flow control. I would like to run the UARTs at much higher baud rates and transfer large amounts of data. This will require flow control.
BTW: Nice…
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Ref #33 #36
Currently, versions have four numbers/fields. I guess they represent relevance from left to right. So, changes in the first field imply breaking changes, the second implies enhancements…
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Hi Stephan,
I used your NEO some years back when developing a CAN Bus core. I loved it. I saw this under RISCV and decided to give it a try. I am porting it to the ProASIC3 starter board. I got it…
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Great work! I really like the UPduino boards!
Interested in yet another RISC-V SoC for the Board? ;)
https://github.com/stnolting/neorv32
It is a full-scale `rv32imc` + *privileged architect…