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On 2019-06-25 on #tomu on IRC, @xobs wrote:
> I need to collapse all the branches down to one and make subdirectories. Possibly throwing away history? Or maybe keep the history in the other branches.…
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usb device is recognized as:
"Tomu Bootloader V2.0-rc4"
but there are no drivers ? and no instructions how to deal with driver installation
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I'm not too familiar with make.
I want to read
`fomu/verilog-blink/Makefile`
to understand the Verilog-to-uploaded binary design flow.
However, the Makefile contains about 65 lines of variable…
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Would be awesome if one could use this great toolchain build for the iCEBreaker FPGA board as well. Also, that would enable the WTFgpa workshops/tutorial to support Windows users, who are currently le…
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In the `litex/workshop.py` and `litex/workshop_rgb.py` examples, I often have to retry reads and writes via the `wishbone-tool` to work around `BridgeError(USBError(Pipe))`. This is happening on box L…
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This is to prepare for possibly extending my own use of Common Lisp for composing.
The end result may be a further extension of csound-extended, including a cross-platform environment similar to Cs…
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## Details
* Read the Docs project URL: N/A
* Build URL (if applicable): N/A
* Read the Docs username (if applicable): xobs
## Expected Result
I received an email that contained the text `T…
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**Description**
for the last 3 weeks, one staging VM has been constantly crashing, at least once a day.
the big difference with other nodes is they have XFS while this one uses EXTFS as bac…
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# Background
Yosys has recently grown the ability to partially infer ICE40 DSP blocks. This works for some Verilog code, but it is not yet at the same level as the proprietary tools when it comes …
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According to the readme a `dfu-util -e` has to be executed after downloading an image to start the new bitstream.
In my experience, running the riscv-blink on a fomu hacker board the program immedi…