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To make localization more smooth. I think we can considering use fpga-shell to serve as standard shim. This can ease the maintaining burden, and make new platform supports more easy.
So my roadmap …
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Hello,
I have not been able to find any TRD for a U250 DPU based on DPUCADF8H. The u200 example for the waa resnet50 is a good baseline, but I need to deploy my app on the Azure cloud which uses a U2…
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Hello!
I run the XRT/test/xrt/13_add_one example. It runs smooothly in hw type. BUT not in sw_emu type. Idont know why.
I use v++ to compile cl kernel to xo file and link it to xclbin file in sw_em…
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In a new end to end example, we try to evaluate tfhe-rs-bool code on an FPGA. To communicate with an Xilinx Alveo FPGA we use the XRT library.
There is a problem during the initialisation of the FP…
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Hi, @eugene-tarassov
I am trying to use U280, but the QSFP pins of U280 is very different from those of U250(according to alveo-u280-xdc, u280 does not have qsfp0_fs[1:0], qsfp0_resetl, qsfp0_refclk…
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Hi,
I am using Alveo U50 board. I am trying to run the ml-suite tensorflow example. I have tried command line as well as Jupyter notebook. I get the same error (show below).
My board is powere…
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Hi,
Just wonder how hard it is to port to U250. Would U250 be supported in the future?
Best,
Yang
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Hello, World!
We are a group intending to accelerate some Pytorch operations on Xilinx UltraScale FPGAs. However, we are a little lost to where to begin to port the functions.
From what we could…
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### Comment:
We only package the userspace bits in the conda package. How does someone know that they have the correct version of the system stuff installed?
Should they:
1. look at the output o…
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Hey, I want to build litex project with ethernet peripheral. I succesfully builded project and generated bit file. I'm trying to loading boot.json file but I got this error.
![image](https://github.…