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Add support for all floating operators:
add, mul, sub
le, lt, ge, gt, neq, neq, neg, sqr, flr, ceil, abs, min, max
div, rem
log, exp, pow, sqrt
sin, cos, tan, asin, acos, atan2, tanh
These are…
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@rdaly525 I fetched the upstream of coreir, checked out dev and tried to build the testbench with a new floating point test, but when I did ```make test``` I got a testbench failure. The output is bel…
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https://github.com/David-Durst/aetherling/blob/sim_issues/tests/helper_test_readyvalid.py#L54
It would be incredibly helpful if this worked. (in addition to not segfaulting. The segfaulting issue i…
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- [x] Replace verilog backend with verilogAST
- [x] Replace metadata["verilog"] with concrete verilogAST definition
- [ ] Replace verilog definitions of coreir/corebit with verilogAST
- [ ] Linking…
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- [x] Cheat sheet/language spec (ala Chisel's cheat sheet https://inst.eecs.berkeley.edu/~cs250/sp17/handouts/chisel-cheatsheet3.pdf), Raj
* [magma cheat sheet](https://github.com/phanrahan/magma/b…
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See https://github.com/rdaly525/coreir/blob/master/include/coreir/definitions/coreVerilog.hpp
These are expected based on https://github.com/StanfordAHA/Primitives/blob/master/coreirprims.csv#L9-L1…
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The following code
```python
class Foo(m.Circuit):
T = m.Array[8, m.Bits[6]]
S = m.Array[4, m.Bits[6]]
io = m.IO(
I=m.In(T),
O=m.Out(S),
)
io.O @= io.I…
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Not sure why coreir and verilator examples are in this repo.
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commonlib's serializer has a count port (https://github.com/David-Durst/coreir/blob/aetherlingMultipleParallelism/src/libs/commonlib.cpp#L1435)
I use serializer in my streamify (https://github.com/…
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https://github.com/David-Durst/aetherling/blob/sim_issues/tests/helper_test_readyvalid.py#L54
This causes CoreIR to segfault and the simulator to stop. This shouldn't be a segfault. Not sure if thi…