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Really, gen_mappings should not be tied to coreir explicitly. In essence it is computing rewrite rules from an arbitrary IR to another arbitrary IR.
This will make it easier to do write a bunch of …
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Add support for all floating operators:
add, mul, sub
le, lt, ge, gt, neq, neq, neg, sqr, flr, ceil, abs, min, max
div, rem
log, exp, pow, sqrt
sin, cos, tan, asin, acos, atan2, tanh
These are…
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```bash
cd coreir
git checkout determinism
make clean
make install -j
pip install delegator.py pytest
while pytest tests/binary/test_concat.py; do :; done # should eventually fail
```
Conte…
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https://github.com/David-Durst/aetherling/blob/sim_issues/tests/helper_test_readyvalid.py#L54
It would be incredibly helpful if this worked. (in addition to not segfaulting. The segfaulting issue i…
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Verilog source example
```verilog
// counter.v
module vcounter(input CLK, output [2:0] O);
reg [2:0] O;
always @(posedge CLK) begin
O
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commonlib's serializer has a count port (https://github.com/David-Durst/coreir/blob/aetherlingMultipleParallelism/src/libs/commonlib.cpp#L1435)
I use serializer in my streamify (https://github.com/…
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```
❯ cgra-mapper test_DefineSub16.json test_DefineSub16_mapped.json
Loading test_DefineSub16.json
Running Pass: rungenerators
In Run Generators
Done running generators
Running Pass: verifyinput…
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The hack to poke an internal verilog signal corresponding to a coreir register no longer works: https://github.com/leonardt/fault/blob/master/fault/wrapper.py#L141-L147
Need to refer to the generat…
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```RecursionError: maximum recursion depth exceeded while calling a Python object
Exception ignored in: '_pydevd_frame_eval.pydevd_frame_evaluator_darwin_36_64.get_bytecode_while_frame_eval'
Recursi…
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See https://github.com/rdaly525/coreir/blob/master/include/coreir/definitions/coreVerilog.hpp
These are expected based on https://github.com/StanfordAHA/Primitives/blob/master/coreirprims.csv#L9-L1…