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Envrionment: Ubuntu20.04, Vitis 2020.2, platform=xilinx_zcu102_base_202020_1
Hello, I'm new to HLS deisgn and attracted by this repository. I've written a lightweight project and successfully synth…
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Hi, I'm a student interested in FPGA and want to learn more about SDR, especially AD936X based ones. I wonder if it's possible to have AD936X extension boards for low-cost FPGA platforms like the PYNQ…
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## Suggestion/Feature Request
For many FPGA platforms there exists a method of inserting a proxy block of memory inside the compiled bitstream, and then replacing this proxy with different blocks o…
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BFLOAT16 is a new floating-point format. It's a 16-bit floating point format with an 8 bit exponent and 7 bit mantissa (vs 5 bit exponent, 11 bit mantissa of a half-precision float which is currently …
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PCIe interconnect with multiple PCIe Endpoints and hosts (FPGA, DPU, CPU, GPU, ...) can be organized in several topologies.
A NTB implementation for FPGA will enable several scenarios like
- fail…
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I performed the following profiling on my sketch, MKR4000 vs MKR1000. The sketch used is the very same on MKR4000 and MK1000, except for conditional compilation to include the right WiFi header file f…
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I am attempting to build the torus kernel for the LINPACK benchmark, but the build errors out in the link stage due to an invalid port mapping. I'm not sure I understand why this issue is occuring, bu…
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### Describe the bug
SYCL kernels are identified by their kernel name, which means kernel names have to be globally unique. This requirement is enforced within translation units, but not globally.
#…
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Hi there,
i need to implement an synthesizer, which should be controlled by the fpga. We bought the bladerf-micro thinking, that this interface would be doable at the expansion port.
Unfortunately, …
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### This isn't an urgent matter at all, I'm just posting for future discussion.
**Is your feature request related to a problem? Please describe.**
Problem: Distributing software for Linux platforms …