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After cloning, I run the icebreaker.py script in the soc folder with both --debug and --flash option, then with either and with none. I get the following error on Ubuntu 18.04
Warning: Wire top.ua…
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The apio and icestorm template projects each contain an example `top.v`, but `icecube2_template` doesn't. For consistency it ought to.
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LUTs in a tile can be cascaded together into a chain, useful for making a shift register style thing.
From http://www.clifford.at/icestorm/logic_tile.html
> Each LUT i has four input wires lutff_i…
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To install icestorm on macOS 10.15.6 I had to install gsed with homebrew and change sed to gsed in icetools/icestorm/icebox/Makefile
gsed parses the -i option differently.
Also yosys, iverilog(ica…
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I've noticed this happens after you compile it and install it too
```
📦[alex@asahi-krun ~]$ box64 ~/box64/tests/bash
Dynarec for ARM64, with extension: ASIMD AES CRC32 PMULL ATOMICS SHA1 SHA2 USCAT…
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I have a design that fails initial placement. This is mostly because of incompatible CE lines for the flipflops and it is for a LP384 which doesn't have a lot of resources and I'm trying to pack 330 L…
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I've had good success with the ice40up5k and have completed two projects with it, but for my latest project I require an FPGA with more pins, and not wanting to look at BGA construction, I've settled …
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git log
`commit f34d5ffb5ec5a9ca0356516ef4c1d4883f07ac96 (HEAD -> master, origin/master, origin/HEAD)`
pyhton3 python3 foboot-bitstream.py --revision pvt
```
Suffix successfully added to fi…
20Mhz updated
4 years ago
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Now that IceStorm has documented the timing for these devices (and in fact can generate a nice static timing report via icetime), would you consider adding timing-driven P&R to arachne? We really nee…
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### Zig Version
0.11.0-dev.2249+dcdb87836
### Steps to Reproduce and Observed Behavior
On a 2021 14-inch MBP (M1 Pro), Ventura 13.2, run:
```
$ zig targets | jq '.native.cpu.name'
"apple_a14"
`…