icebreaker-fpga icebreaker-litex-examples issues - Githubissues

icebreaker-fpga / icebreaker-litex-examples

Example litex Risc-V SOC and some example code projects in multiple languages.

62 stars 18 forks source link

issues

Newest

Newest Most commented Recently updated Oldest Least commented Least recently updated

SoC Appears to no longer fit inside Ice40 FPGA

#14 JamesTimothyMeech closed 1 year ago
13
Attempting to run the SoC build script produces "name 'LiteXModule' is not defined`" error

#13 JamesTimothyMeech closed 1 year ago
2
c-riscv-blink/Makefile: Check for riscv32-unknown-elf-gcc in different paths.

#12 Zottel closed 1 year ago
1
wishbone-util hangs

#11 slagernate opened 1 year ago
0
toolchain setup instructions

#10 securelyfitz closed 2 years ago
1
Update LiteX examples

#9 gregdavill closed 2 years ago
10
gdb breakpoints for c-riscv-blink

#8 jogi91 opened 3 years ago
0
LiteX submodule version points to unreachable URL

#7 d0ntrash opened 3 years ago
5
Rust binary (after objcopy) too large

#6 crepererum opened 3 years ago
6
Fix some minor wording in README.md

#5 mithro closed 3 years ago
1
c-riscv-blink: wishbone error

#4 pdp7 closed 4 years ago
1
icebreaker.py error

#3 dadede opened 4 years ago
8
Use 32-bit MMIO registers

#2 Disasm closed 4 years ago
3
Generate memory.x, use riscv/riscv-rt for the Rust example, use cargo run

#1 Disasm closed 4 years ago
1