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This repository was created by merging the following resources:
- [ghdl/ghdl-systemc-fosdem16](https://github.com/ghdl/ghdl-systemc-fosdem16) (ghdl/ghdl-systemc-fosdem16#1).
- The content from sec…
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I have created a small example design which illustrates a problem I have when upgrading to MyHDL 0.10. The Verilog created from this example is missing a "reg" declaration of slc_out.
The same exam…
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I see lots of discussion in MyHDL forum. Just want to know that is there any branch or version for MyHDL that support convert which retain the hierarchical structure in python while convert to Verilog…
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Hey Alex,
tks again for the IPs, bothering you again about usage! do you know how to get some waves of `udp_complete` module or if there's a diagram of how to drive the interfaces on this module? …
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I'm trying to drive the reset and halt lines on a m68k processor. These lines are bi-directional so I only want to have Z or 0 on my pin from the FPGA. I don't care about them if the m68k does ever dr…
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The [example](http://docs.myhdl.org/en/stable/manual/conversion_examples.html#user-defined-code) given in the manual is failing both for verilog and vhdl with 0.9.0 and 1.0dev.
Also input ports are …
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On simulation `ConcatSignal` requires more than one argument [1] but it gives a error when converting to vhdl/verilog.
> Not supported: extra positional arguments
## System information
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I can't imagine this is correct. However when one is trying to verify the RTL sims of a testbench, they always seem to exit after the myhdl sim is run.
If the output of the myhdl sim is nothing, i…
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Hi,I have some problems about the AXI_DMA module,what does parameter OFFSET_WIDTH,OFFSET_MASK,ADDR_MASK and CYCLE_COUNT_WIDTH mean?Can I ask you for a AXI_DMA_RD_TB.V and AXI_DMA_WR_TB.V file？Maybe ca…
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Summary
I have a block ram memory I am trying to write. It is meant to be a drop in replacement for the standard block rams that vivado generates, but parameterisable and syntheisable (in addition t…